CE24 - Micro et nanotechnologies pour le traitement de l’information et la communication 2023

Automatic Cross-Layer Synthesis of High Performance, (Ultra-)Low Power Hardware Implementations – HiLoDaNets

Submission summary

High throughput data and signal processing applications can be specified preferably by dataflow networks, as these naturally allow the exploitation of parallelism. State of the art system-level design approaches aid an algorithm designer to compile a dataflow network to a set of processors, or to synthesize the network directly in hardware for achieving high processing speeds. However, embedded systems have additional requirements: Safe operation, even in an environment of intermittent power shortages, and in general (ultra-)low power requirements. Altogether, these requirements seem to be contradictory.
HiLoDa Nets tries to attack such conflict in requirements by introducing, exploiting and integrating for the first time emerging FeFET technology for the design of actor networks. In particular, circuit devices being able to operate in mixed volatile/non-volatile mode of operation will be characterized, modelled and designed. By combining the system-level concept of dataflow which is based on self-scheduled activations of computations with emerging CMOS-compatible FeFET technology to persist result data upon actor firings, inactive actors or even subnets shall inherit the capability of self-powering (down and wakeup).
HiLoDa nets will be able to combine high clock speed data processing of each synthesized actor circuit in power-on mode and automatic state retention using FeFET technology in power-off mode, self-triggered during time intervals of either data unavailability or power shortage. We will develop a fully automatic cross-layer synthesis and design space exploration from system-level dataflow specification to optimized FeFET devices-based circuit implementation in terms of throughput, circuit cost, energy savings and endurance. Finally, HiLoDa nets will be compared to conventional CMOS technology implementations for applications such as spiking neural networks. Low expected shutdown and recovery latencies from power shortages will be evaluated.

Project coordination

Bertrand VILQUIN (INSTITUT DES NANOTECHNOLOGIES DE LYON)

The author of this summary is the project coordinator, who is responsible for the content of this summary. The ANR declines any responsibility as for its contents.

Partnership

INL INSTITUT DES NANOTECHNOLOGIES DE LYON

Help of the ANR 260,224 euros
Beginning and duration of the scientific project: February 2024 - 36 Months

Useful links

Explorez notre base de projets financés

 

 

ANR makes available its datasets on funded projects, click here to find more.

Sign up for the latest news:
Subscribe to our newsletter