Turbo decoding with Less Energy, Area and more Parallelism for higher throughput – TurboLEAP

B5G applications call for higher throughput (TP), lower power consumption and more scalability which translates to stringent constraints for the Forward Error Correction. For next generation standards, Turbo codes are losing ground to LDPC and Polar codes despite their inherent rate-flexibility and recent progress in achieved performance. Indeed, Turbo codes have been seen at a disadvantage for high-TP applications exhibiting a TP-gap of several orders of magnitude. In recent works, the TurboLEAP team was able to bridge this gap by up to 2 orders of magnitude compared to prior art. This project intends to go even further demonstrating hardware implementations with a TP in the order of Tb/s. The leap to Tb/s goes through: 1)Improving area and power efficiency by applying new simplified decoding algorithms and devising original pipelined architectures. 2)Supporting flexibly long frame sizes(>1000 bits) while preserving large coding gains through interleaver design and spatial coupling.