CE25 - Infrastructures de communication hautes performances (réseau, calcul et stockage), Sciences et technologies logicielles 2018

SHNoC: A Reliable Multi-Technologies Network-on-Chip – SHNoC

Submission summary

Since few years we are witnessing the emergence of manycore architectures, namely to the implementation of massive parallelism on a single chip. Associated with the shrinking size of the transistors, announced reaching an 11nm technology on 2020, these manycore architectures should reach the integration of thousand of hetero- geneous cores allowing huge parallel computation capabilities suitable for High Performance Computing (HPC) and embedded systems. These parallelism capabilities obviously generate an enormous amount of data exchanges making the communication medium a key element of the overall performance of the system.
Massively parallel manycore architectures are showing the scalability limits of electrical NoCs (ENoCs) that suffer when facing thousands of cores. This generates an increase in the latency, hence in the power consumption. Theses degradations are also amplified while the size of the wire decreases. Technology evolution has allowed for the integration of silicon photonics and wireless on- chip communications, creating Optical and Wireless NoCs (ONoCs and WNoCs, respectively) paradigms. The recent publications highlight advantages and drawbacks for each technology: WNoCs are efficient for broadcast, ONoCs have low latency and high integrated density (throughput/cm^2) but inefficient in multicast, and ENoC still efficient for average size of NoC.
In this context, this project proposes to associate these three technologies. Each NoC technology possesses par- ticular and complementary advantages allowing to efficiently route messages depending on their profile: short or long distance, uni- or multi-cast. Moreover, given the shrinking size of the transistors, on-chip architectures become more sensitive to faults. As the access of ONoC and WNoC are handled through shared interfaces, they become critic resources, and any fault can severely degrade the performance of the whole communication archi- tecture. This project proposes to integrate fault tolerance mechanisms to protect theses access points. For this purpose, we will use self-detection and self-diagnosis mechanisms to turn the faulty non-correctable access points in a degraded mode.
A Scalable Hybrid NoC (SHNoC) associating electric, optic and wireless communication NoCs to take advantage of each technology is proposed in this project. Adaptive Quality of Service will be proposed to efficiently route the messages on the most efficient technology with respect to constraints. Indeed, the QoS will propose guarantees on latency, throughput or energy regarding the needs of the application. This QoS protocol will take into account any degraded access point to adapt its decisions on run-time.

Project coordination

Cédric Killian (Institut de Recherche en Informatique et Systèmes Aléatoires)

The author of this summary is the project coordinator, who is responsible for the content of this summary. The ANR declines any responsibility as for its contents.

Partnership

IRISA Institut de Recherche en Informatique et Systèmes Aléatoires

Help of the ANR 234,360 euros
Beginning and duration of the scientific project: January 2019 - 48 Months

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