Low-Energy On-chip Pre-processing for Activity Recognition – LEOPAR

Several key points need to be addressed during the project. They follow the general design flow of an ASIC, from high-level software simulations all the way to the circuit fabrication and validation.
In order to validate the proposed concepts, a high-level model of the hardware pre-processing unit has to be developed. It has to mimic the behavior of the internal signals of both the feature extraction and the classification units as close as possible. This means that an original simulation environment has to be developed in order to respect the continuous-time property of the signal, in the feature extraction unit. The designed processing chain must then be validated taking into account the system global energy consumption, the circuit silicon area and an estimation of the energy gain for the sensor. In the particular case of audio signal recognition, a thorough study of acoustic models has to be done in order to extract the relevant features maximizing the effectiveness of the pre-processing units depending on the defined criteria.
Once the technical choices have been validated through simulations, they have to go through a hardware validation process. This process is necessary to ensure the possibility of a real-time operation of the pre-processing unit on real inputs. This phase implies the design of several individual hardware prototypes, for the feature extraction block and the classification unit. These prototypes can be designed on an FPGA or use existing ASICs implementing only a part of the system, e.g. an ASIC implementing a flexible clique-based neural network.
After hardware validation, the pre-processing unit will be entirely integrated on a single IC, using the CMOS 28-nm FDSOI technology node. The tests and validation of this IC will be done in regards of the metric defined during the high-level simulation validation. Finally, a global system demonstration board will be set to show the pre-processing unit effectiveness in a real context of application.

The final objective of the LEOPAR project would be the design and fabrication of a complete energy-efficient “wake-on-feature” demonstrator, including a pre-processing unit prototype ASIC in advanced CMOS technologies, able to prove the effectiveness of the global proposed scheme, i.e. real-time extraction of characteristic features of audio signals using non-conventional techniques such as event-driven digital processing and associative memories.

The global focus is the decrease of the global energy consumption of a sensor node by several decades. Target numbers for the proposed groundbreaking integrated circuit structures are an average consumption lower than 1 µW, an energy consumption for a single classification of less than 1 nJ, a silicon area of less than 0.5 mm² and a latency of less than 1 ms while adding configurability to address many applications.

At the national level, communication about the project will be centered on workshops dealing with the thematic of “Near-sensor computing” or embedded computations, organized by the GdR SOC2 and the French branch of IEEE Circuits and Systems Society, in which permanent members of the project are involved.
Finally, the valorization of the scientific results will be made through high impact international conferences and journals. In the circuit design domain, journals such as IEEE Journal of Solid-State Circuits or IEEE Transactions on Circuits and Systems I: Regular Papers, as well as the IEEE International Solid-State Circuit Conference or the IEEE European Solid-State Circuit Conference will be targeted.
Patents about event-driven computational unit and low-energy classification unit will also be targeted.

The emerging “Internet of Things” and ambient intelligence growth is faced with massive amounts of data to be transferred from connected portable devices to central computation units that process data from multiple sensors. Depending on the application, the devices communicate wirelessly the entirety of the data sets or embed generic computing resources to process them locally. Decreasing the energy consumption of the devices must be a priority to increase the battery lifetime. Since the communication interface or the embedded processor are the most energy-hungry parts of the sensor nodes, the “Near-Sensor Computing” concept aims at pre-processing the input data in order to limit either the amount of data to transmit or the number of computations in the processor.
The LEOPAR project aims at designing the so-called pre-processing unit in order to determine the signal relevance for the targeted application. This is done in two steps: first the signal features are extracted and are classified in a second step to determine the signal relevance. These functions are destined to be integrated on-chip using processing techniques in rupture with the state-of-the-art leveraging the benefits of both analog and digital signal processing. The performance of the pre-processing unit will be evaluated in terms of combined energy consumption and silicon area occupation at the unit level in standalone, as well as at the global system level.