Logic Elementary Gate Overstacked – LEGO

The Vertical GAA NW FET, a disruptive technology, allows to move from 2D to a truly 3D layout configuration, with the gate length of the transistor defined vertically. Vertical integration is a particularly attractive approach because of its intrinsic 3D nature, which is more favorable to scale the contacted gate pitch i.e. scaling of the gate length and contact area.
The LEGO project is intended to fill the gap between device research and innovative logic circuit implementation

Three European Follow up Project proposals : I_LEGO, LEGO4TALK and FVLLMONTI

2019 03 29 : Drafting of the proposal I_LEGO (Intelligent Si based on Logic Elements using Gate Overstacking) in response to the call for projects H2020-ICT-06-2019, proposal number: 871629. This proposal is based on the original idea of the ANR LEGO research program and was also supported by an MRSEI grant.
2019 10 03 : Decision : Rejection

2020 06 03 : Drafting of the proposal LEGO4TALK (Logic Elements using Gate Overstacking for Translation And Language acKnowledgement) in response to the call for project H2020-FETOPEN-2018-2019-2020-01, Proposal number: 964413. This proposal is based on the original idea of the ANR LEGO research program.
2020 10 27 : Decision : Rejection

2020 06 17 : Drafting of the proposal FVLLMONTI (Ferroelectric Vertical Low energy Low latency low volume Modules fOr Neural network Transformers In 3D) in response to the call for project H2020-FETPROACT-2018-2020 (FET Proactive – Boosting emerging technologies). This proposal is based on the original idea of the ANR LEGO research program.
2020 09 24 : Decision : Accepted
2021 01 01 : FVLLMONTI starting date

Two invited papers in internationals conferences:

? C. Maneux, I. O’Connor, S. Le Beux, G. Larrieu, “New logic paradigms based on vertical NanoWire FET: The coming LEGO technology”, École d'hiver Francophone sur les Technologies de Conception des Systèmes Embarqués Hétérogènes, FETCH 2019, 27 janv. 2019, Louvain la neuve, Belgique.
? I. O'Connor, A. Poittevin, A. Bosio, S. Le Beux, C. Marchand, G. Larrieu, C. Maneux, «Vertical nanowire FETs and their impact on 3D computing architectures«, Invited paper, 28th IFIP/IEEE International Conference on Very Large Scale Integration ,VLSI-SoC 2020, 5-9 October 2020, Salt Lake City, UT, USA.

• develop a lightweight design kit including compact models to support the circuit design flow
• prove enhanced logic functionality and logic circuit operation in terms of propagation delay, dynamic and static power consumption, resilience to temperature and supply voltage variation
• assess the technology roadmap improvements and the associated logic performance metrics.

1. [INVITED] C. Maneux, I. O’Connor, S. Le Beux, G. Larrieu, “New logic paradigms based on vertical NanoWire FET: The coming LEGO technology”, École d'hiver Francophone sur les Technologies de Conception des Systèmes Embarqués Hétérogènes, FETCH, 27 janv. 2019, Louvain la neuve, Belgique.
2. C. Mukherjee, G. Larrieu, C. Maneux, «Compact Modeling of 3D Vertical Junctionless Gate-all-around Silicon Nanowire Transistors«, EuroSOI-ULIS 2020, Caen (France).
3. [INVITED] I. O'Connor, A. Poittevin, A. Bosio, S. Le Beux, C. Marchand, G. Larrieu, C. Maneux, «Vertical nanowire FETs and their impact on 3D computing architectures« (invited), in Special Session on Implementation Needs for Tomorrow’s Computing, IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SOC), Salt Lake City (UT), USA [virtual], 5-9 October 2020
4. A. Poittevin, C. Mukherjee, I. O’Connor, C. Maneux, G.
Larrieu, A. Kumar, F. Marc, A. Lecestre, M. Deng, S. Le Beux, «3D logic cells design and results based on Vertical NWFET technology including tied compact model,« IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SOC), Salt Lake City (UT), USA [virtual], 5-9 October 2020

Data size and functionality requirements for computing are increasing, according to the expectation that hardware performance will continue to improve, irrespective of the actual implementation. This is particularly true for emerging distributed computing paradigms for the Internet of Things, such as Edge Computing and Fog Computing, which are placing extraordinarily stringent constraints on computing hardware performances. However, the end of the roadmapped technological scaling is anticipated in a few technology nodes, mainly for cost reasons down to the 7nm FinFET gate length node.
In this context, vertical integration is an attractive approach thanks to its intrinsic 3D nature, which is more favorable to scale the contacted gate pitch. The vertical NW (nanowire) array based transistor is much easier to manufacture because the gate length is simply defined by the thickness of the deposited gate material. Further, enhanced functionality can be achieved with doping techniques leading to the stacking of N and P type transistors. Accordingly, new architectures are mandatory. Many conceptual ideas already exist for non-conventional logic circuit design. They are usually based on emerging device technologies which have been developed and extensively characterized at laboratory level. However, due to the broad gap between device research and technology optimization, no vertical logic circuit demonstrators exist. The LEGO project is intended to fill the gap between device research and innovative logic circuit implementation through the following objectives:
- demonstrate the proof of concept of stacked vertical NWFET for non-conventional logic circuit
- develop a design kit including compact models to support the circuit design flow
- prove enhanced logic functionality and logic circuit operation in terms of propagation delay, dynamic and static power consumption, resilience to temperature and supply voltage variation
- assess the technology roadmap improvements and the associated logic performance metrics.
The partners of the highly qualified and motivated LEGO consortium are especially relevant to address this disruptive design-technology co-optimization: three academic laboratories (LAAS, IMS, INL) bringing appropriate contributions based on excellent expertise and high-level research in the fields of NW fabrication, electrical characterization, compact modelling, and innovative circuit design. The unique technological skills, with five patents held by LAAS on the scaled vertical NW transistor process technology, offer a great opportunity for success in this very high gain project. Previous work, initial developments and past collaborations mean that there are no showstoppers and that the consortium is confident that the project will succeed. The main risks are therefore the delay in technology fabrication. This will be mitigated by the use of initial technology, which enable exploration of novel circuit designs without searching for optimal parameter values. Two logic styles that are well suited to regular fabrics of vertical NWFETs using in LAAS technology:
o pass-transistor logic (PTL) using uniform and hybrid n/p NWFETs
o majority inverter graphs (MIG), enabled by PTL, using multiple electrode NWFETs

Huge gains in silicon area are expected through the combination of extremely small elementary device footprint and minimal device usage with MIG and PTL design styles. For example, a 1-bit full-adder can be built in PTL with just 4 vertical hybrid n/p nanowires instead of 31 nanowires in standard logic. Such 10x reductions in complexity will lead to similar gains in energy consumption and delay. Therefore, the LEGO project specific objectives are:
- Ground-breaking stacked vertical n- and p- NW Field Effect transistor
- 3D innovative elementary logic building blocks based on stacked n- and p- NW FET
- 4-bit ALU using the actual implementation of two logic styles based on stacked vertical NWFETs.