Self-Adaptive, Energy Efficient High Performance Embedded Computing, UAV case study – HPeC

HPeC Strategy: 1) Separate HPeC (Mission) / Autopilot (Navigation) Boards 2) Architecture model based on Tiles implementing IP from Libraries or High-Level Synthesis and adaptation by means of Dynamic partial reconfiguration of FPGA (DPR) 3) Adaptation based on two complementary levels (mission and SoC) Level 1 : Reliable Control of Scheduling Sequences including HW reconfigurations with a controller generated with formal discrete controller synthesis techniques Level 2: Stochastic methods (Dynamic Markov Decision Processs + Bayesian Networks) for online decision making according to random events Internal (failures risks, failures …) and External (weather, obstacles, objet / target detection, …)

- Tile-based Architecture on FPGA Altera/Intel - Automatic generation of configuration automata for sequences (scheduling + DPR) - Implementation of applications for the UAV demonstrator on Cyclone V Board (image processing: tracking, landing area detection, stabilisation, Sensor fusion : obstacle detection, stabilisation, decision : MDP) - Design of HPeC Board - New Method (BFM) modular and scalable combining Bayesian Networks for diagnostic and MDP for mission planning.

Next steps: - Demonstrator setup based on simulation and HPeC board embedded on the UAV - High Level tools for the design and the programmation of self-adaptive system on chip.

[ZER17a] S. Zermani, C. Dezan, C. Hireche, R. Euler, J-Ph. Diguet, Embedded context aware diagnosis for a UAV SoC platform, Microprocessors and Microsystems (MICPRO) Journal, Vol. 51, pp. 185 - 197, 2017 2017 [GUE17a] S. Mak-Karé Gueye, E.Rutten and J-Ph. Diguet, Autonomic Management of Missions and Reconfigurations in FPGA-based Embedded System, 11th NASA/ESA Conf. on Adaptive Hardware and Systems (AHS), Pasadena, CA, USA, July, 2017. [ABD17a] E.M. Abdali, F. Berry, M. Pelcat, J-Ph. Diguet and F. Palumbo, Exploring the Performance of Partially Reconfigurable Point-to-Point Interconnects, 12th Int. Symp. on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), , Madrid, Spain, July, 2017. [ABD17b] E.M. Abdali, A. W. Hanniche, M. Pelcat, J-Ph. Diguet and F. Berry, Hardware Acceleration of the Tracking Learning Detection (TLD) Algorithm on FPGA, 11th Int. Conf. On Distributed Cameras (ICDSC), Stanford Univ., USA, Sep. 2017. [HIR17a] C. Hireche, C. Dezan and J-Ph. Diguet, Online Diagnosis Updates for Embedded Health Management,  6th Mediterranean Conf. on Embedded Computing (MECO'17), Montenegro, June 2017. [ROD17a] M. Rodrigues, D.F. Pigatto, J.V.C. Fontes, A.S.R. Pinto, J-Ph. Diguet, K.R. Branco, UAV Integration Into IoIT: Opportunities and Challenges, ICAS 2017, Barcelona.

The HPeC project aims at demonstrating the relevancy of self-adaptive hardware architectures to respond to the growing demands of high performance computing, in an increasing class of embedded systems that also have demanding footprint and energy efficiency constraints. This is typically the kind of embedded system we have in small autonomous systems like UAVs, that require high computing capabilities to perceive the environment (e.g embedded vision) and make decisions about task to execute according to uncertainties related to the environment, safety critical systems, the health of the system and processing results (e.g. identified object).
The HPeC thesis is to consider that it is possible to design a reconfigurable hardware architecture optimized for a given set of applications that will be activated with an undetermined order and based on a number of basic functional blocks that can be large but finite. The choices of these functions (e.g. 2D convolution), which are shared by the applications, will define the granularity of the architecture. Considering a set of possible hardware/software configurations, satisfying the objectives in terms of performances and energy efficiency, the system must choose at runtime the best configuration according to mission uncertainties.
We propose to address the work with a three-tiered approach. The first tier is the question of the model of the reconfigurable architecture that must accommodate the set of applications with the appropriate granularity level in a tradeoff between sharing opportunities (fine) and efficiency (coarse).
The second tier is the dynamic reconfiguration that allows implementing dedicated hardware architecture while sharing resources between application tasks in such a way that energy efficiency and performance are optimized. The sharing (temporal and/or spatial) will be implemented with a deterministic method by means of a Finite State Machine that results from the synthesis of a discrete controller. This synthesis will be made offline with a formal approach that will guarantee the reliable behavior of the embedded system, which is essential in the area of autonomous systems. According to events such as task completion, deadlines and current use of resources, the controller will reach a state that corresponds to a unique HW/SW configuration.
The third tier deals with the management of random events (e.g. obstacle detection, failure) to be handled by the mission manager (e.g. path planning, forced landing). This manager will first evaluate the state of the system and of the environment in a probabilistic way. In the second step, it will make decisions based on a policy (e.g. minimum risk). The result of this decision is a list of tasks with specific priority levels that will be the input of the HW/SW configuration controller.
The HPeC team has chosen a challenging application domain to demonstrate the relevancy of the approach. The selected context is a number of small autonomous UAVs with embedded vision capabilities.
The team comprises all required domains of expertise: reconfigurable / adaptive HW architectures and associated CAD tools (Lab-STICC/Institut Pascal), architectures for embedded vision (Ins. Pascal, Inpixal), controller synthesis and autonomic computing (INRIA) and probabilistic methods (Gipsa-Lab/Lab-STICC). HPeC will also have the support of UAV experts of ARCAA (QUT, Brisbane, Australia) who already cooperate with Lab-STICC in a CNRS PICS program.
Finally, the HPeC aims to realize a real demonstrator that will allow implementing the expected contributions of the project (reconfigurable architecture, configuration controller, mission manager). It will take the form of a Hybrid-FPGA based board to be embedded on a small UAV that will perform reconnaissance missions with different scenarios (simple to complex ones) to demonstrate adaptation capabilities. The board will be the first step for Inpixal towards new smartcameras designed for UAV market.