Reliable and Reconfigurable Dynamic Architecture – ARDyT

Today, advances in CMOS technology are hampered because of physical and economic limits. In particular, the shrinking transistor size implies a reduction in yield and reliability of SoC due to the presence (variability) or appearing ("aging") of physical defects in the circuit. This change brings a revolution in design practice and requires the design of fault-tolerant circuits or with faults detection capabilities. The answer to this challenge has implications for devices models, architecture, dependability and CAD tools. In terms of complex systems implementation, reconfigurable FPGA circuits are now part of the mainstream thanks to their flexibility, performances and high number of integrated resources. FPGAs enter new fields of applications such as aeronautics, military, automotive or confined control thanks to their ability to be remotely updated. However, these fields of applications correspond to harsh environments (cosmic radiation, ionizing, electromagnetic noise) and with high fault-tolerance requirements. Current FPGAs are not adapted to these environments, except for specific circuits that have been hardened but at a very high cost overhead, which makes them less interesting from an economic point of view.

The purpose of the ARDyT project is to provide a complete environment for the design of a fault-tolerant and self-adaptable platform. Then, a platform architecture, its programming environment and management methodologies for diagnosis, testability and reliability have to be defined and implemented. The considered techniques are exempt from the use of hardened components for terrestrial and aeronautics applications for the design of low-cost solutions. The ARDyT platform will provide a European alternative to import ITAR constraints for fault- tolerant reconfigurable architectures.

We intend to develop a dynamically reconfigurable embedded architecture with specific support mechanisms for the management of reliability. If the recovery aspect of dependable systems is relatively well studied at present, detection and diagnosis aspects remain to be developed. The use of reconfiguration combined with advanced fault detection techniques will then consider a self-adaptable fault-tolerant architecture (i.e., a self-healing architecture that is able to correct its own functioning in the presence of errors). The project is organized around three main axes. The first axis is the study and implementation of the reconfigurable hardware with integrated resources for improving testability and physical diagnosis of the circuit. The architecture design requires the development of a software environment enabling its exploitation. The second focus of the project concerns the definition and development of a set of design tools (synthesis, placement, routing) for the proposed architecture. This software framework will also synthesize applications with the insertion of high-level diagnostic mechanisms (such as duplication) to improve reliability of the whole system. This approach will allow to achieve a self-testing architecture, to synthesize control of architecture for an application with optimized diagnosis, and finally to insert breakpoints in the application to produce a monitored platform. Finally, the architecture and tools will incorporate advanced reliability mechanisms. The last axis of the project concerns the definition of test and tolerance methodologies adapted to dynamic architectures and using the intrinsic properties of this type of support. This study will impact on one hand the architecture resources to simplify fault-tolerance implementation, and on the other hand tools to achieve synthesis for reliability.