Enhanced MRAM Yield et Reliability – EMYR

According to ITRS, embedded memories occupy a major part of the area of a typical system-on-chip (SOC). Many diversified applications require the SOC to integrate non-volatile memories. Although flash memory is widely used today, it needs high voltage for Program and Erase operations and has reliability issues that are hard to handle, increasing the cost of circuit design and process integration. The industry has been trying to find a good alternative (non-volatile memory) that can replace flash memories. Possible candidates include magnetic random access memory (MRAM), ferroelectric random access memory (FeRAM), Ovonic memory, etc. Among them, MRAM has been identified as having the potential to become a universal on-chip memory. It is a high-speed, low-voltage, and high-density non-volatile memory with virtually unlimited Read/Write endurance.
However, defect densities, failure mechanisms and fault models of MRAMs are yet to be investigated. Only few papers can be found in the literature and most of them are only considering the problem of write disturbance. Moreover, one study has considered the defect analysis and fault modeling of failure mechanisms that may affect the MRAM structure. However, this study does not use any industrial data for MRAM modeling and defect location / type / density.

The EMYR project is focused on the issues mentioned above with the goal to improve the yield and reliability of MRAMs. A complete strategy will be proposed to test and mask manufacturing and reliability defects. Due to the intrinsic immunity of MRAMs to transient faults, only wear-out induced reliability defects will be considered.
The main objectives of this work are to develop:
- Fault models and test strategies that are well adapted to the specificity of MRAM failure mechanisms. Resulting test strategies will be integrated into a programmable Built-In Self-Test (BIST) engine.
- Efficient MRAM repair mechanisms for masking manufacturing and wear-out induced defects. Such mechanisms will provide a more optimal use of redundant memory resources like redundant rows and columns. Particularly, the approaches available in the state-of-the-art for the management of redundant memory columns are sub-optimal and we strongly believe that a lot of improvement space is left.

The EMYR project is scheduled to facilitate scientific fallout and provide CROCUS Technology with strong technical and economic benefits. Solutions with both short and medium-term applicability:
- Short-term BIST and BISR schemes will be developed for a fast integration into CROCUS Technology products. The main purpose here is to use generic fault models with the constraint to cover a wide range of defect densities. Our intention here is to have the short-term BIST and BISR schemes implemented in silicon and use this experience to consolidate and refine these schemes.
- Consolidated BIST and BISR schemes will be proposed in a second phase of the project based on the CROCUS Technology feedback and roadmap.
The EMYR consortium is composed of (a) CROCUS Technology which is the only French industrial actor that is active in the field of MRAMs, (b) LIRMM which is recognized as a European expert in the areas of memory testing and (c) CEA LIST which is an emerging actor in the field of embedded system reliability.