Dispositifs Supraconducteurs en Silicium et Germanium "haut de gamme" – SUNISIDEUP

To meet the objectives, the project is organized in four workpackages: Management (WP1), Material synthesis (WP2), S/Sm contacts and device integration (WP3) and Low temperature investigations and quantum manipulation (WP4) with dedicated and focused sets of tasks. The success of the project will rely upon the possibility to efficiently share devices. The follow-up of process steps will be the main task of the management workpackage together with the organization of regular meetings either in Grenoble or Paris-Saclay. In practice, wafers will be processed first at the LETI up the point where the following steps require new tools or are not compatible with the LETI constraints. In that case, the samples will not come back tyo the LETI and will have to be further processed up to the contact level. This procedure has been used in the past for many project and do not show any particular risks. The rest of the project is organized in rather logical and progressive scheme. First, the material properties will be studied in WP2 (material synthesis). This WP2 will mostly focused on the superconducting materials (silicides and heavily doped superconducting silicon) used for silicon devices. Germanium tank wafer and GeOI wafers will also be processed within this WP2. Then, test devices that includes TLM (Transverse Length Methods) and Kevin cross devices will be fabricated (WP3) and measured at low temperature to extract the electronic transparency of the S/Sm interface (WP4). This first campaign of measurements will allow extracting the conditions to build superconducting transistors (WP3). One the process parameters found, real transistors with superconducting contacts will be produced. Those from silicon will be processed from the LETI FDSOI base line. For Ge based devices, the nanofabrication will be done using the open access PTA clean room at the CEA/Grenoble (WP3). The resonators will be fabricated in parallel either at the PTA or at the C2N (WP3) and fully characterized at low temperature (WP4). The final gatemon geometry will be implemented at the PTA and/or C2N from transistors and resonators previously studied (WP3). Final quantum manipulation will be performed by the end of the project (WP4). Such rather complex measurements will be performed at PHELIQS in close collaboration with Olivier Buisson and N. Roch from the CNRS Neel institute close by (WP4).

The obtained results strongly depend on the semiconducting material.

For silicon, we have focused our work on material science in order to develop and stabilize superconducting film growth that are fully compatible with the CMOS technology. We have studied three different silicides (V3Si, PtSi and CoSi2) (hal-03166557, hal-03364021). The first two have shown very good superconducting properties but suffered from integration issues. In the standard process to fabricate a transistor device, the metallic material (V,Pt or Co) is first deposited and then annealed to create the silicides where it is in contact with the silicon. The unreacted metal is then etched away using chemical etching that is highly selective with the silicide. The process flow do not exist for V3Si and its development within the project would have required too much resources. For PtSi after unsuccessful attempts, we have decided to delegate the development to our Swedish partner in the quantera project SIQUOS (hal-04580892). Finally, the process for CoSi2 has been fully developed at the CEA-LETI during the Sunisideup project. For heavily doped superconducting silicon layer (hal-04442429, hal-03985419), we have demonstrated the process of laser annealing using an industrial tool on 300 mm at the CEA-LETI and compared the results with academic tool used at C2N. This work has revealed the importance of short laser pulses under high vaccum. In a complementary project (MATQU) we have developed the integration of CoSi2 transistors. In the mean time we have performed preliminary measurements on old devices made from PtSi silicide (hal-04085518).

Concerning devices based on germanium heterostructures, we have developed the full fabrication process of superconducting transistors with the Sunisideup project (PhD thesis C. Tangchingchai). The devices have been processed from SiGe/Ge wafers given by the partner LETI. All the remaining fabrication steps have been done at the PTA clean room with the financial support of SUNISIDEuP. During the time of the project, we have obtained very good superconducting transistors which show a non-dissipative current that is tunable by an electrostatic gate. Such JoFET (Josephson Field Effect Transistor) is the building block of various circuits that has be subsequently studied. In the framework of SUNISIDEuP, we have first investigated in details the Josephson effect and how superconducting quantum coherence can be transferred and preserved though a Ge channel (https://arxiv.org/abs/2311.15371). In a second work, we have studied the quantum properties of two JoFETs and demonstrated the potential of such new devices for future development of gate tunable superconducting qubits (https://arxiv.org/abs/2311.15371). Finally, thanks to the outcomes of SUNISIDEuP for Ge based JoFET, we have recently obtained our first gate tunable superconducting qubits that is under investigation. This work being supported by the RobustSuperQ PEPR project.

Clear perspectives on superconducting transistors are now clearly opened. New project have been accepted thanks to SUNISIDEuP (see below MATQU, JoGATE, SIQUOS) and some are under evaluation : FLiQSS (EIC Pathfinder Open HORIZON-EIC-2024-PATHFINDEROPEN-01-01), inGeQT (ANR-PCRI Japan).