Optimal Control of Inverters in Embedded Systems – COPTON

The aging of the capacitors is analyzed in a controlled both electrically and thermally environment. For this, choppers are used either at a constant or variable duty ratio and each chopper has a capacitor stressed by a controlled RMS current. Each capacitor is instrumented to measure the surface temperature and the assembly is placed in an oven whose inside temperature is kept constant at 70 ° C.
At regular time intervals, the system is stopped to make an impedance analysis of the capacitors and thus observe the evolution of this impedance as a function of operation time (at different temperatures for this analysis : 25 , 60 and 80 ° C ).
On this experimental basis , we compared different models proposed in the literature. We can then use this model and adapt it to make it usable in a computer in real time to perform a monitoring capacitors inside an inverter to perform a self-test and possibly detect an imminent failure. More interestingly , we can deduce from the estimated state of the capacitor a control strategy of the inverter best suited to maximizing its life (i.e. minimization of aging).

Among all models of capacitors studied, we have chosen a model that is actually derived from those conventionally used for batteries. It better reflects the actual behavior of the components we use. Indeed, the equivalent circuits commonly used for modeling electrolytic capacitors differ significantly at certain frequencies from the measured behavior. This model introduces a diffusion phenomenon (non-integer order model) which can be explained by the etching of the anode of capacitors, thereby increasing their effective surface but is not likely to be effective at all frequencies.

Based on these models, we will implement on a dedicated target in real time a capacitor model sufficiently faithful to the behavior of real components but still simple enough to not consume too many resources in the monitoring body which will then be used to develop a optimum control of the inverter. This will in effect share an FPGA between an estimator of the state of the capacitor and a sophisticated PWM controller that will use information from the estimator to develop a strategy which aims primarily to minimize aging capacitors.

1. A Methodology for Studying Aluminium Electrolytic Capacitors Wear-out in Automotive Cases, R. Cousseau, N. Patin, E. Monmasson, L. Idkhajine, Conférence EPE’2013, Lille, France, Sept. 2013.
2. Advanced Electric Model of Aluminum Electrolytic Capacitor with Diffusive Element, R. Cousseau, N. Patin, E. Monmasson, L. Idkhajine, Conférence Electrimacs’2014, Valence, Espagne, Mai 2014.
3. Une méthodologie pour l'étude de l'usure des condensateurs aluminium électrolytiques dans un véhicules urbain, R. Cousseau, Conférence JCGE’2013, Saint-Nazaire, 5-6 juin 2013
4. Modélisation électrique et thermique des condensateurs électrolytiques en vue de l’analyse de leur vieillissement dans un contexte de traction électrique, N. Patin, R. Cousseau, E. Monmasson, L. Idkhajine, C. Forgez, Conférence SGE’2014, 8-9 juillet 2014

The proposed project aims at designing optimal control strategies dedicated to inverters in embedded applications. In this general context, this work is focused on the electrical stress generated by the inverter on dc link capacitors. This point is a crucial aspect of inverter dimensioning because these components occupy a large volume in inverters (especially low voltage and high currents converters). Moreover, they are expensive and fragile.
Previous studies allowed to develop several strategies (quite simple from the algorithmic point of view) minimizing the rms current in these capacitors but it is not proved that such a solution is optimal for a longer lifespan of these components.
Thus, an alternative solution to the strict minimization of this current is the design of controller allowing to maintain a constant stress even if the converter works in a varying operation mode. This kind of technique will avoid or limit damages due to thermal fatigue mechanisms. A predictive control strategy is good candidate for this purpose but the price to pay with such a technique is its algorithmic complexity not being really compatible with a real-time implementation, at least in a DSP. Conversely, FPGAs are particularly adapted to this kind of problem due to their parallel processing capabilities perfectly matched to the algorithm to implement. The key challenges of this study will relate, on one hand, to the design of a controller architecture using in a reasoned way the FPGA resources (trade-off between consumed resources and calculation time) and, on the other hand, to the efficient real-time identification of system parameters (especially on the dc bus), essential to the implementation of an accurate predictive controller.