SINGLE ELECTRON DEVICE INTEGRATION ON CMOS TECHNOLOGY – SEDIMOS

Since the creation of the integrated circuit, more than 4 decades ago, a tenfold increase in computing performance is achieved every 5 years. The most significant impact of this trend is the continuing decrease of cost-per-chip which has led to significant improvement in economic productivity and overall quality of life though the proliferation of computers, communication and electronics in general. This outstanding improvement is essentially due to the scaling down of the CMOS technology (Complementary Metal Oxide Semiconductor). The International Technology Roadmap for Semiconductors anticipates that to continue this trend, innovative solutions must be introduced for post-CMOS technology within the next 10 years. To achieve this, a tremendous research effort on emerging devices or materials must be deployed to bring these technologies to an acceptable maturity level. These emerging research devices will need to be compatible with existing CMOS technologies in order to be heterogeneously integrated with CMOS circuits and capitalize on the established semiconductor industry. Also, these devices have to address the issue of power dissipation (<100 W/cm2) to be considered for a viable solution. Members of the Center of Excellence in Information Engineering (CEGI) at the Université de Sherbrooke, Canada have developed a radically new approach for the fabrication of single electron transistors (SETs) one of the emerging research devices proposed for post-CMOS technology. This engineering breakthrough has allowed to achieve SET with low impedance and extraordinarily small capacitances (paving the way for high-speed memories and logic devices), and concomitant reliable operation 100°C above room temperature. Research at INL (INSA Lyon, France) focuses on the modelling and the characterisation of emerging nanodevices (SET, SEM, RTD etc.) and also contributes to original technological process (e.g. AFM nanomanipulation). Since few years, these two labs have developed important collaborations within the International Laboratory for Nanotechnologies and Nanosystems (LIA LN2). The scientific objective of this project consists in stacking Single Electron Devices (transistors - SETs or memories - SEMs) on a standard CMOS technology and providing the tools to make use of such hybrid SET-CMOS technology (device / interconnect models etc.). This project is presented by INL (McF Francis Calmon, Professor Abdalkader Souifi, McF Nicolas Baboux, Professor Brice Gauthier, Engineer David Albertini) and CEGI (Professors Dominique Drouin, Jacques Beauvais and Serge Charlebois) with the support of STMicroelectronics, Crolles, France (CMOS wafer supply) and IBM Bromont, Canada (SED-CMOS die packaging). This research program will address the issue of energy consumption by capitalizing on the previously developed high power efficiency single electron device platform; 1) to heterogeneously integrated SET with CMOS technology from chip to package; 2) to investigate new electronics functionalities; 3) to increase performance of logic and memory devices. The impact of this research is ranging from more energy efficient portable electronic (Laptop, MP3 player, Cellular phone) to universal computer memory (single memory type regrouping DRAM, hard-disk and flash memory).