Dynamic vectorization for heterogeneous multi-core processors with single instruction set – DYVE
Most of today's computer systems have CPU cores and GPU cores on the same chip. Though both are general-purpose, CPUs and GPUs still have fundamentally different software stacks and programming models, starting from the instruction set architecture. Indeed, GPUs rely on static vectorization of parallel applications, which demands vector instruction sets instead of CPU scalar instruction sets. We advocate a disruptive change in both CPU and GPU architecture by introducing Dynamic Vectorization at the hardware level.
Dynamic Vectorization will combine the efficiency of GPUs with the programmability and compatibility of CPUs by bringing them together into heterogeneous general-purpose multi-cores. It will enable processor architectures of the next decades to provide (1) high performance on sequential program sections thanks to latency-optimized cores, (2) energy-efficiency on parallel sections thanks to throughput-optimized cores, (3) programmability, binary compatibility and portability.
Project coordination
Caroline Collange (Centre de Recherche Inria Rennes - Bretagne Atlantique)
The author of this summary is the project coordinator, who is responsible for the content of this summary. The ANR declines any responsibility as for its contents.
Partner
Inria Rennes - Bretagne Atlantique Centre de Recherche Inria Rennes - Bretagne Atlantique
Help of the ANR 260,281 euros
Beginning and duration of the scientific project:
March 2020
- 42 Months