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The UDEC project aims at defining and developing an efficient and high performance universal channel decoder architecture model for emerging and future digital communication systems. In order to address the large variety of channel coding options and flavors specified in existing and coming digital

The economical constraints linked to the cost and market adaptation impose the integration of processor cores in the VLSI circuits. The flexibility that the System on a Chip "SoC" provides, suffers from a lack of performances for certain classes of application which need both speed and flexibility

The sea of transistors available on one chip opens the door to many new image and video processing applications for the security and the transportation industries, with different trade-offs between raw per-formance, power and cost. Large reconfigurable chips (FPGA) such as Virtex, or even embedded F

Operating with self-organized or random assemblies of nanodevices resulting from a bottom-up assembly would make it possible to stop the explosion of the integrated circuits manufacturing costs. Nevertheless, the programming and the use of such assemblies to fulfill a given function require to set

Embedded systems which support image processing have to cope with the challenging dilemma of the computing capacities versus the power consumption. A typical digital signal processing architecture, assigns an entire image to a single processor, but as real-time image processing applications have tre

In the context of high end mobile appliances for the multimedia and telecom market, the use of ad-hoc accelerators for both computation and communication is absolutely necessary due to the power efficiency requirements. Considering a platform as a configurable SW and HW environment, the HOSPI projec

The HODISS project addresses the problem of global synchronization of complex systems on chip (SOC), e.g., with a solid-state multiprocessor. Given the characteristics of modern VLSI technologies, the designer partitions big circuits into many isochronous zones, each one behaving like a classical

For last few years, evolution of SoC and increasing density of integration has proposed to target the constraints of performance, consumption and design cost/time by inter-connecting a growing number of IP blocks. This complexity added to the increasing heterogeneity of these architectures leads us

In various application domains emerging requirements leads to the definition of new architectures for electronic embedded systems, both for software and hardware parts. For example, in the automotive context, investigated solutions correspond to network of processing elements, distributed in the v

ADAM stands for “Adaptive Dynamic Architecture for MP2SoCs”. It is a direct spin-off of the ARAMIS project submitted last year to the ANR, and put on a waiting list in December 2006. ADAM is a prospective research project that directly addresses the hot topic of MP2SoC self-adaptability to alter

Today, System-on-chip (SoC) and System-in-package (SiP) become more and more complex and include not only digital blocks but also analogue parts, radio frequency (RF) communication capabilities as well as sensor/actuators. This is due to advances in semiconductor technology and the market demands to

The SFINCS project (Semi-Formal INstrumentation for Circuits and Systems) investigates and develops new technologies for SoC validation. SFINCS addresses Assertion-Based Verification (ABV). During the design process, assertions (written for instance in PSL or in SVA) help describe: ? the results ex