P2N - Nanotechnologies et nanosystèmes

InAs Ultra Thin Film-Body Metal Oxide Semiconductor Heterostructure FET on Silicon wafer – MOSINAS

InAs Ultra Thin Film-Body Metal Oxide Semiconductor Heterostructure FET on Silicon substrate

The objective of the project is to reduce the consumption of N-channel MOSFET for introduction of a high mobility III-V material. The use of these materials should reduce the operating voltage in sub-of 0.5V regime.

Reduction of power consumption in N-MOSFET technology using a III-V channel

The issues are pursuing Moore's Law. The limitation concerns the power consumption of transistors. The use of III-V materials should allow to reduce consumption while maintaining the same or better electrical performance. <br /> <br /> <br /> <br /> <br /> <br /> <br /> <br /> <br /> <br /> <br /> <br /> <br /> <br /> <br /> <br />The issues of the project are pursuing Moore's Law, A bottleneck is the power consumption of transistors. The use of III-V materials should allow to reduce consumption while maintaining the same electrical performance.

The chosen material is InAs due to it very high mobility. The mobility of bulk InAs is 40 times higher than silicon. To reduce leakage current and to maintain good control of the electron in the channel, ultra thin body structure is chosen. Several important issues will be addressed from a technological point of view: the growth of III-V materials on 300mm silicon substrate; preparing N-MOSFET sub-50 nm; the use of the selective growth of III-V and a silicide-like technology to form the ohmic contacts; the development of a high quality high-k oxide on III-V. All these technological steps will be characterized. A task simulation comes in extra technology to optimize structures and to interprete electrical results.

The first results concern: the growth of GaAs on 300mm silicon wafer with good morphological quality. A densified oxide Al2O3 with low interface defect down few 10E11 / cm²EV. The selective growth of III-V on III-V.

The next challenge is to fabricate the first sub-50 nm transistor combining all technological steps developed in the project.

On July 2015: 1 RICL, 6 CICL, 6 CNCL

Since a few years, the CMOS Si technology faces a power consumption crisis because the “historical scaling law”, implying proportionality between the power supply voltage VDD and the node half-pitch dimension, has not been maintained since the 90nm node (around 2005). This has lead to both various material solutions and tricks in integration processes, especially in the Front-End part of the CMOS; among them, the introduction of strained Si channels and of the High-K Metal Gate stack and to the use of thin body films. Nevertheless, new rupture solution must be envisioned for next technological nodes, as stated by ITRS.
Within this context, low voltage FETs, that can operate at much lower voltage than Si MOSFETs, would be a welcome solution to the power crisis. MOSINAS is an industrial research project which aims at introducing InAs as the channel material of n-type MOSFETs. Indeed, from the high electron mobility and injection velocity in III-V semiconductors, higher on-state currents can be expected and can be used to decrease VDD/VT, so reducing leakage and overall power consumption. InAs material has the highest electron mobility of III-V (close to InSb) and will offer the possibility of co-integration with GaSb materials as the P-channel. GaSb offers the best hole mobility of III-V.
The main objective of the project is the study and fabrication of UltraThin Body MOSFET with buried InAs channel on Silicon, called UTB-MOSHFET (UltraThin Body MOS Heterostructure FET) on 300mm silicon wafer. This architecture is preferred to the FinFET, due to today easier technological integration. Indeed planar technology such as TB-MOSHFET is an intermediate step, required to confirm the future III-V technologies on Silicon.
This project is a follow-up of a previous one supported by the ANR (MOS35) which focused on low power analog applications on III-V substrates and has demonstrated high-frequency capability of InGaAs-based MOSFETs. The experience gained in MOS35 leads us to this new proposal going far beyond with 4 key aspects, namely:
i) The insertion of a thin upper barrier layer between the channel and the oxide (heterostructure)
ii) The use of a thin body InAs channel on a large bandgap material
iii) For the source-drain region, the suppression of the implantation incompatible with low thermal budget and the development of new contact process
iiii) Evaluation of monolithic InAs integration on 300mm silicon wafers using buffered layers.
As a by-product of this project, for RF applications, the good transport properties of III-Vs allow state-of-the-art cutoff frequencies and noise properties. Co-integration of III-V materials on Silicon will offer the field of RF applications with low cost, what makes III-V MOSFETs promising candidates for applications covering the "More than Moore" domain.
This project is clearly in line with the objectives of ANR « axe thématique 1 : miniaturisation » and matched with « l’introduction de matériaux de haute mobilité type III-V .

Project coordinator

Monsieur Sylvain Bollaert (Institut d'Electronique, de Microélectronique et de Nanotechnologie)

The author of this summary is the project coordinator, who is responsible for the content of this summary. The ANR declines any responsibility as for its contents.

Partner

ST C2 SAS STMicroelectronics (Crolles2) SAS
PSud/IEF Université Paris-Sud 11 / Institut d'Electronique Fondamentale
IMEP Institut de Microélectronique Electromagnétisme et Photonique
CEA-LETI Commissariat à l'Energie Atomique et aux Energies Alternatives - Centre de Grenoble
LTM Laboratoire des Technologies de la Microélectronique
IEMN Institut d'Electronique, de Microélectronique et de Nanotechnologie

Help of the ANR 997,656 euros
Beginning and duration of the scientific project: December 2013 - 48 Months

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