DS07 - Société de l'information et de la communication

Energy-first Design of LDPC Codes and Decoders – EF-FECtive

Energy-first design of LDPC codes and decoders

EF-FECtive aims to develop low-density parity-check (LDPC) codes and decoder circuits that together provide a 10x reduction in the energy consumption of decoders, while preserving equivalent communication performance. This will be achieved through contributions to both communication theory and VLSI system design, with the ultimate objective of demonstrating a decoder ASIC that can tolerate circuit faults while operating in the energy-efficient near-threshold regime.


EF-FECtive (Energy-First Forward Error-Correction) aims to advance the state-of-the-art in the energy efficiency of LDPC decoders through fundamental contributions to code design methods and VLSI decoder design, and by establishing a close interaction between coding theory and implementation constraints. One of the key aspect that differentiates EF-FECtive from existing approaches is its ambition to combine competences from hardware design and from coding theory to obtain energy models that are both accurate from an implementation point of view and tractable for code optimization. Furthermore, EF-FECtive aims to provide a solution to the variability problem in near-threshold CMOS circuits by designing codes and decoders that can tolerate occasional timing violations without degrading their error-correction performance. While fault-tolerant LDPC decoders have been studied before, existing literature does not provide a clear path towards practical implementations. EF-FECtive will close this gap by demonstrating an actual LDPC decoder integrated circuit operating reliably in the near-threshold regime thanks to its fault-tolerant properties. To the best of our knowledge, this will be the first demonstration of an ECC decoder ASIC that tolerates circuit faults in its operation.<br /><br />The project aims at understanding and improving the energy usage of LDPC decoders. The first part of the project focus on the energy consumption of conventional VLSI decoders and aims to study the impact of the code design on the energy consumption of the decoder, and the manner in which the energy consumption grows as the communication channel quality is degraded. The second part of the project is more disruptive in nature and aim to demonstrate energy gains of an order of magnitude with respect to the SoA by exploiting synergies between the code, the decoder architecture, and a VLSI implementation operated in the near-threshold regime.

WP1 - ASIC development:
This Work Package will contain the main engineering tasks that are required to support the experimental aspect of the project. WP1 will be responsible for designing a flexible decoder architectural template that can be configured for various situations of interest (different levels of parallelism and code structures), to generate placed-and-routed circuit models of this architecture, and to facilitate “virtual” energy measurements on the designs by creating scripts that interface with commercial CAD tools. In addition, this WP will prepare one decoder architecture of interest for fabrication.

WP2 - Energy Models:
This Work Package will be responsible for proposing energy models for standard decoders that operate reliably, and deviation-vs-energy models for quasi-synchronous decoders that allow occasional circuit faults.
Energy models for reliable implementations will first be constructed based on the simulation of final placed & routed circuits obtained in WP1, which will permit a large number of energy measurements made on several systems. WP2 will then characterize faulty decoder implementations in order to obtain deviation vs energy models.

WP3 - Code and decoder parameter optimization:
This Work Package will develop the theoretical framework and the technical solutions that will permit to design powerful LDPC codes for energy efficient hardware implementations. WP3 will first introduce theoretical tools that will permit to characterize the performance of LDPC codes and decoders with deviations. WP3 will then develop the code design process will then consist of jointly optimizing the code parameters (the protograph and the codeword length), the decoder parameters (number of iterations), and the operating conditions of the hardware implementation (supply voltage and clock period) under deviation-vs-energy models. In order to develop the code design method,

In WP1, we introduced a novel LDPC decoder architecture. This architecture allows a great flexibility in computation operation scheduling.

Then, in collaboration between WP1 and WP3, we proposed a novel LDPC code construction, well-suited for the decoder architecture developed in WP1. This construction provides protograph based quasy-cyclic LDPC codes. In addition to standard performance criterion, this construction takes into account the decoder architecture constraints such as memory complexity and latency.

In WP3, we introduced an optimization method for protographs. This method provides protograph that minimize the decoder energy consumption while ensuring a good decoding performance.

In WP2, we developed a complete framework in order to measure the energy consumption of all the decoder circuit components (processors, memories, control unit, etc.). This framework was realized with CAD tools. After a statistical analysis of the circuit energy consumption, we observed that the circuit energy consumption is almost equally shared between memory units and processing units.

To finish, in WP3, we introduced a novel density evolution method. Our method allows to treat asymmetric fault models, while standard approaches only consider symmetric models.

In WP1, it remains to finish the design of the ASIC circuit.
In WP2, we now have a complete framework to measure the energy consumption of the different parts of the circuit. We now want to develop statistical models of energy consumption versus amount of faults introduced in the circuit. We want to develop models that are both accurate and suitable for performance analysis in WP3.
In WP3, we would like to extend our protograph optimization method in order to take into account the faults introduced by the circuit.

Mohamed Yaoumi, François Leduc-Primeau, Elsa Dupraz, Frederic Guilloud, Optimization of Protograph LDPC Codes based on High-Level Energy Models, accepted at 16th International Symposium on Wireless Communication Systems (ISWCS), Oulu, Finland, August 2019
Elsa Dupraz, Lav R. Varshney, Binary Recursive Estimation on Noisy Hardware, accepted at International Symposium on Information Theory (ISIT), Paris, France, July 2019
Elsa Dupraz, François Leduc-Primeau, François Gagnon, High-Throughput LDPC Decoding Achieved by Code and Architecture Co-Design, 10th International Symposium on Turbo Codes and Iterative Information Processing (ISTC), Hong Kong, December 2018
Mohamed Yaoumi, Elsa Dupraz, Franc¸ois Leduc-Primeau, Frederic Guilloud, Optimisation de la Consommation d’Energie pour des Codes LDPC Construits a` Partir de Protographes, accepté à Colloque GRETSI, September 2019

Error-correction codes are used in the vast majority of communication systems because they allow a significant reduction of the transmitter power. Although many different coding schemes that can approach the Shannon limit on transmit power are known, the capability of practical systems is often limited by the energy consumption of the decoder. This constraint is being mentioned as a key performance metric in the ongoing 5G standardization process in order to deal with the great increase in the number of users and in the throughput while keeping a constant energy budget. In addition to the practical need for low-energy receivers, recent theoretical results have shown that in order to get arbitrarily close to the Shannon limit, the decoding circuit must consume an arbitrarily large amount of energy. This shows that optimizing the trade-off of coding gain versus decoding energy is fundamental in the channel coding problem.

EF-FECtive aims to develop low-density parity-check (LDPC) codes and decoder circuits that together provide a 10x reduction in the energy consumption of decoders, while preserving equivalent communication performance. This will be achieved through contributions to both communication theory and VLSI system design, with the ultimate objective of demonstrating a decoder ASIC that can tolerate circuit faults while operating in the energy-efficient near-threshold regime.

First, an approach to model the energy consumption of LDPC decoders combining an analysis of the decoding algorithm with simulations of circuit models will be developed. Based on these energy models, theoretical tools will be created to design LDPC codes and decoder circuits that minimize the decoding energy. Then, decoder implementations operated in the near-threshold regime will be studied. In this regime, extremely energy-efficient operation can be achieved, but maintaining fast processing performance requires the system to tolerate faulty computations. By developing accurate models of the effect of faults on the decoder and of its energy consumption, methods will be proposed to jointly optimize the LDPC code construction, the implementation parameters, and the amount of circuit faults allowed to drastically reduce the decoding energy. Finally, an ASIC prototype of the decoder will be designed, fabricated and tested to demonstrate the energy gains in practice.

Project coordination

Elsa Dupraz (Ecole Nationale Supérieure Mines Telecom Atlantique Bretagne Pays de la Loire)

The author of this summary is the project coordinator, who is responsible for the content of this summary. The ANR declines any responsibility as for its contents.


IMT Atlantique Ecole Nationale Supérieure Mines Telecom Atlantique Bretagne Pays de la Loire

Help of the ANR 212,328 euros
Beginning and duration of the scientific project: December 2017 - 36 Months

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