Development of a fast processing electronics for track trigger for Hadron Collider Experiments – FastTrack

ATLAS FTK and CMS L1 tracking use a two-step AM-based algorithm. The AM is used as a real time filter comparing the incoming physics event to a bank of pre-computed trajectories (patterns). Then the event data filtered and sorted by the AM is processed by the FPGA for the final track fit. The parameters, pattern bank and track fit algorithm are tailored to the specific needs of the experiment.
The AMchip05/06 is designed using a mixed full custom / standard cells approach: the memory element is designed in full custom in order to achieve maximal optimization for power consumption and density; the match and control logic are developed in standard cells in order to be able to efficiently simulate, synthesize, place and route using modern automated electronics CAD tools.
The AMchip05 and AMchip06 are designed in 65 nm, a mature yet performant technology, since we want to use them immediately for FTK and CMS prototypes. AMchip07 is designed in 28 nm, a more performant technology, since we want to have this chip available for future application (FTK upgrade, CMS L1 tracking, non-HEP applications).
The PCB boards use Xilinx FPGAs (series 6 and 7). We develop the firmware using standard Xilinx tools and both Verilog and VHDL languages. Each specific application has its own firmwares.
The software side is written in C++ and python, it is integrated with the general frameworks of each experiment.

The associative memory chip AM05 has been designed and delivered. Actually the chip incorporated some but not all of the features described in the proposal. In exchange of this limitation we had an early opportunity to have the chip produced sooner than expected and to save funds for AM07 (AM06 is just the larger version of AM05 for FTK installation, no new features). We expect to finance and produce AM07 prototypes in the second part of the project.
The AM05 test card has been designed and produced and the corresponding firmware has been completed. The AMcard-FMC has also been completed in a version without the onboard FPGA, in order to simplify the development of the AM-FPGA communication firmware.
The CMS system-simulation code has been delivered

The AMchip implements a computing function not available in any other commercial devices allowing the development of very powerful real time algorithms.
The AMchip05 and AMchip06 are among the largest and most complex projects in our community using the 65 nm technology. The AMchip07 prototypes are the very first computational chips developed in 28 nm in our community.
The AMchip-FMC card has beed developed for the specific needs of our applications, but is in fact an FMC compliant card that can be used in any FMC socket and it is a reference desing for general purpose AM-based devices.

- Presentation of the project at the Workshop on Intelligent Trackers conference (May 2014 - Philadelphia, USA) : indico.cern.ch/event/293354/
- Presentation of the AMchip05 chip at the EPS Conference on High Energy Physics, (July 22-29 2015, Vienna, Austria) cds.cern.ch/record/2045498/

The goal of the project is to develop an extremely fast but compact processor, with supercomputer performances, for pattern recognition, data reduction and interpretation. The proposed hardware features flexibility for potential applications in a wide range of fields, from triggering in high energy physics to DNA sequence alignment. In general, any artificial intelligence application based on massive pattern recognition could largely benefit from the foreseen architecture, provided data are suitably prepared and formatted.

To this end we propose the design and the production of a standard-cell CMOS chip in a deep sub-micron commercial process. This chip, based on associative memories (AM), will be able to process at very high rate large amounts of data, like for example the information coming from high-energy physics tracking detectors. The designed AM chips will be paired with an FPGA (Field Programmable Gate Array) on dedicated processing boards which will perform high-level analyses on the filtered data at unprecedented speed.

The primary aim of the FastTrack project is to demonstrate that this processing unit can perform online track reconstruction of full events at the CERN Large Hadron Collider (LHC) in its High-Luminosity Phase (HL-LHC), when the instantaneous luminosity of the accelerator will be increased by almost a factor ten, to reach several units of 1034 cm-2s-1. Indeed, under these conditions the capability of the LHC experiments ATLAS and CMS to pre-select interesting events inside an enormous background cannot be maintained with the use of standard readout and trigger systems, and online tracking becomes mandatory. Both collaborations plan to include this feature in their respective upgrade programs. This project will allow initiating a strong collaboration between ATLAS and CMS in this domain, resulting in the development of a generic AM-based hardware device usable by both experiments.

Finally, we plan to exploit the potential of these new devices in non-HEP applications. In particular, DNA sequence alignment is a complex procedure where the use of an AM chip might lead to significant improvements. Demonstrating this would be a significant breakthrough in the field, and will open new scientific directions for AM-chip technology dissemination.