JCJC SIMI 3 - JCJC - SIMI 3 - Matériels et logiciels pour les systèmes et les communications

Selective Area Molecular Beam Epitaxy for the realization of an Antimony-based inverter with Complementary Tunnel Field Effect Transistors – SAMBA

Complementary Tunnel Field Effect Transistors for low power consumption electronics

Can we overcome the fundamental limits of CMOS technology combining antimony based III-V material properties and selective area epitaxy?

Tunnel effect for beyond CMOS ?

The increase in the processor capabilities resulting from the continued miniaturization of the silicon based CMOS transistor technology has reached its limit in term of overall power dissipation. To go further would require a further reduction of the operating voltage not compatible with the fundamental limits of the CMOS technology based on thermionic injection. To get electron device able to switch from the “off-state” to the “on-state” with a sub-threshold swing better than 60 mV/decade at room temperature, new devices based on other type of injection mechanism have to be developed.<br />The Tunnel Field Effect Transistor (TFET), based on field effect control of interband tunneling, is one possible solution to overcome these limitations but it suffers from a low Ion current using large bandgap silicon based materials and technologies. For this reason, III-V material based devices have been considered recently by a lot of renowned international labs and industries. Among the III-V materials, Sb-based heterostructures are particularly suitable for interband tunneling device since they offer the possibility of highly staggered heterojunctions, increasing significantly the tunnel probably and thus the ON-state current.<br />Within this context, the objective of the SAMBA project is to investigate the potential of the “6.1 Å family” (InAs, GaSb, AlGaSb) for the realization of TFET devices working at a sub-0.25 V supply voltage, what would drastically reduce the power consumption of processors. We propose to develop an epitaxial and technological process for the realization of an antimony-based-Complementary-TFET inverter with targeted device characteristics outperforming CMOS technology in term of sub-threshold swing value while keeping an ON-state current at 0.25 V in the range of hundredths of µA/µm.

The technological development achieved within the SAMBA project concerned the fabrication of a vertical tunnel field effect transistor (TFET) with side gates using top-down processing of an AlGaSb/InAs heterostructures, and the selective area growth with molecular beam epitaxy of GaSb/InAs heterostructures on a largely mismatched GaAs substrate for integration strategy.

Concerning the transistor fabrication, the process involves a metamorphic growth of AlGaSb/InAs heterostructures on GaAs substrate, an anisotropic wet chemical etching of the InAs channel, a gate oxide deposition by atomic layer deposition and air-bridge contacts to realize a device based on vertical transport with a double side gate controlling the tunnel injection of electrons from the AlGaSb source to the InAs channel.

Concerning selective are growth, we used molecular beam epitaxy with an atomic hydrogen flux during the growth to improve the quality and the selectivity of GaSb grown on a GaAs substrate patterned with a silicon dioxide mask.

The results obtained in the frame of the SAMBA project concern both the fabrication and characterization of InAs/AlGaSb TFET and selective area growth of these materials by MBE.
Concerning the transistors, we have achieved for the first time a TFET device, with vertical topology and side gates, from an AlGaSb/InAs heterostructure grown on a largely mismatched GaAs substrate. A Source/Drain ON-current larger than 430 µA/µm for VDS=VGS=0.5V has been obtained. With low temperature electrical measurements, we have demonstrated the impact of interface traps between the gate oxide and the InAs channel on the subthreshold slope (SS) of the device. At 77K, where the impact of traps is reduced, SS decreases to 71 mV/decade with an ON/OFF drain current ratio of 6 decades. This trade-off between maximum ON-current and switching efficiency is a record for a TFET based on an AlGaSb/InAs heterostructure grown on GaAs.
The other part of the project concerns selective area epitaxy and the possible integration scheme for antimony based TFET. MOCVD is a technique of choice for selective area growth thanks to the catalytic decomposition of precursors. However, in the project, we have demonstrated that MBE is also a valuable tool for selective growth and it may offer a better control of interfaces together with a lower thermal budget of fabrication. In the case of GaSb, we have shown that the use of an atomic hydrogen flux during the growth improves the selectivity with respect to a silicon dioxide mask. Using this technique, GaSb/InAs nanostructures free for threading dislocations have been grown on a patterned GaAs substrate, the mismatch being accommodated thanks to a regular array of 90° misfit dislocations at the interface between GaSb and GaAs.

The performances of our vertical TFET offer several prospects.
The low temperature electrical characterization of our device has revealed the impact of the interface trap density between InAs and gate stack on the subthreshold slope characteristics. Improving this gate stack with ALD pre-treatment and post-annealing and/or using HfO2 as gate dielectrics should be the first way of investigation. Reducing the InAs body thickness to reach a vertical nanowire topology should also contribute to enhance the switching efficiency of the device. Some attempts using dry etching have been led within the project. 10 nm wide InAs body has been obtained; the difficulty is now to contact these nanostructures.
Another prospect concerns the integration of these device on Silicon. The results obtained with selective area MBE growth of GaSb/InAs nanostructures on GaAs demonstrate the possibility to accommodate very large mismatch with this technique. Combined to the « V-groove » based solution starting the growth on {111} facets of Silicon, this approach may lead to nanostructures free from antiphase domains and threading dislocations.
Eventually, realization of pTFET with these materials still needs to be developed for the fabrication of a CMOS device on Silicon working at very low supply voltage.

Articles:

FAHED M. et al, J. Cryst. Growth (2017) (in press)

CHINNI V.K. et al, IEEE J. Electron Devices Soc. 5, 1 (2017) 53-58

FAHED M. et al, Nanotechnology 27, 50 (2016) 505301

FAHED M. et al, Nanotechnology 26 , 29 (2015) 295301

DESPLANQUE L. et al, Nanotechnology 25, 46 (2014) 465302

Communications:

DESPLANQUE L. et al, 19th European Workshop on Molecular Beam Epitaxy, EuroMBE19, Korobitsyno, Saint Petersburg, Russia, march 19-22, 2017

DESPLANQUE L. et al, Proceedings of Joint 44th Int. Symp. on Compound Semiconductors, ISCS 2017, and 29th Int. Conf. on Indium Phosphide and Related Materials, IPRM 2017, Compound Semiconductor Week, CSW 2017, Berlin, Germany, may 14-18, 2017, to be published

DESPLANQUE L. et al, Proceedings of 26th Int. Conf. on Indium Phosphide and Related Materials, IPRM 2014, Compound Semiconductor Week, CSW 2014, Montpellier, France, may 11-15, 2014, paper Mo-C1-6


FAHED M. et al, 19th Int. Conf. on Molecular Beam Epitaxy, MBE 2016, Montpellier, France, september 4-9, 2016, paper Mo-A2

DESPLANQUE L. et al, 19th Int. Conf. on Molecular Beam Epitaxy, MBE 2016, Montpellier, France, september 4-9, 2016, paper Tu-B7

FAHED M. et al, 15èmes Journées Nano, Micro et Optoélectronique, JNMO 2016, Les Issambres, France, 30 mai-1 juin, 2016

CHINNI V.K. et al, 15èmes Journées Nano, Micro et Optoélectronique, JNMO 2016, Les Issambres, France, 30 mai-1 juin, 2016

CHINNI V. et al, 28th International Conference on Indium Phosphide and Related Materials, IPRM 2016, Toyama, Japan, june 26-30, 2016, paper MoP-IPRM-016


DESPLANQUE L. et al, 28th International Conference on Indium Phosphide and Related Materials, IPRM 2016, Toyama, Japan, june 26-30, 2016, paper MoP-IPRM-002

FAHED M. et al, European Materials Research Society Spring Meeting, E-MRS Spring 2015, Lille, France, may 11-15, 2015, paper I-10.1

DESPLANQUE L. et al,18th Int. Conf. on Molecular Beam Epitaxy, MBE 2014, Flagstaff, AZ, USA, september 7-12, 2014, paper P129

The increase in the processor capabilities resulting from the continued miniaturization of the silicon based CMOS transistor technology has reached its limit in term of overall power dissipation. The main reason for this is that the shrinking of field effect transistors (FET) must respect the simple constant-electric-field scaling rule to get faster switching time along with lower power consumption. But this requires a further reduction of the operating voltage not compatible with the fundamental limits of the CMOS technology based on thermionic injection. To get electron device able to switch from the “off-state” to the “on-state” with a sub-threshold swing better than 60 mV/decade at room temperature, new devices based on other type of injection mechanism have to be developed.

The Tunnel Field Effect Transistor (TFET), based on field effect control of interband tunneling, is one possible solution to overcome these limitations but it suffers from a low Ion current using large bandgap silicon based materials and technologies. For this reason, III-V material based devices have been considered recently by a lot of renowned international labs and industries. Among the III-V materials, Sb-based heterostructures are particularly suitable for interband tunneling device since they offer the possibility of highly staggered heterojunctions, increasing significantly the tunnel probability and thus the ON-state current.

Within this context, the objective of the SAMBA project is to investigate the potential of the “6.1 Å family” (InAs, GaSb, AlGaSb) for the realization of TFET devices working at a sub-0.25 V supply voltage, what would drastically reduce the power consumption of processors. We propose to develop an epitaxial and technological process for the realization of an antimony-based-Complementary-TFET (CTFET) inverter with targeted device characteristics outperforming CMOS technology in term of sub-threshold swing value while keeping an ON-state current at 0.25 V in the range of hundredths of µA/µm.

Simulation of quantum tunneling devices, selective area molecular beam epitaxy of nearly lattice matched InAs, GaSb and AlGaSb materials and deep submicron processing of vertical heterostructures will be combined to achieve a complementary common drain inverter structure with a double side gated channel. Other important aspects to bring this technology to a “beyond CMOS” solution will be considered such as the possible high density of integration, the robustness of the device characteristics against small fluctuations of epitaxial and technological parameters and the integration on standard 300 mm silicon wafers.

Project coordination

Ludovic Desplanque (Institut d'Electronique de Microélectronique et de Nanotechnologie) – Ludovic.Desplanque@IEMN.Univ-Lille1.fr

The author of this summary is the project coordinator, who is responsible for the content of this summary. The ANR declines any responsibility as for its contents.

Partner

IEMN Institut d'Electronique de Microélectronique et de Nanotechnologie

Help of the ANR 271,376 euros
Beginning and duration of the scientific project: January 2013 - 48 Months

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