MRAM/CMOS Hybridization to Secure Cryptographic Algorithms – MISTRAL

MISTRAL is addressing the security of the cryptography embedded in connected objects at its highest standards while keeping concern by the energy footprint. Consequently, MISTRAL aims at proposing innovative research about the MRAM and CMOS hybridization to secure Light Weight Cryptographic (LWC) algorithms with a particular focus on the resistance against physical attacks at lowest energetic impact.

The proposed methodology and estimated results rely on :

* LWC algorithm benchmarking as reference point to compare future results

* Specification of countermeasures against fault attacks taking benefits from MRAM/CMOS hybridization properties

\item LWC algorithm designs : CMOS-based, hybridized and embedding MRAM-based coutermeasures

* Security characterization of the MRAM bitcells : simulation, nanofabrication, characterization and modeling

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In CES 39, MISTRAL takes part of the "Sécurité globale et cybersécurité" topic (8.8) of the ANR AAP2019 work program. More specifically, this project aims to experimentally develop secured schemes to protect objects and embedded systems as listed as key points in "Cybersécurité: liberté et sécurité dans le cyberespace, sécurisation des systèmes d'information, lutte contre la cybercriminalité".This item detailed in the paragraph E.8, "Domaines transverses". Moreover, MISTRAL adresses the topic (5.6), "Modèles numériques, simulation, applications" by leveraging technological solutions of secured embedded systems with MRAM NVM memory and the energy consumption of countermeasures in LWC algorithms.

So far connected objects have been designed and deployed with strong cost and power consumption constraints, postponing security to secondary requirements. Recent successful attacks have proved that the security of IoT will become a major and crucial issue. Technical solutions, like Light Weight Cryptographic (LWC) and countermeasures against physical attacks, have to be designed to bridge the gap between security needs and cost constraints. The implementation of such solutions is a key point for both academic and industrial actors.

MISTRAL is addressing the security of the cryptography embedded in connected objects at its highest standards while keeping concern by the energy footprint. Consequently, the project aims at proposing innovative research about the MRAM and CMOS hybridization to secure LWC algorithms with a particular focus on the resistance against physical attacks at lowest energetic impact.

The proposed methodology and estimated results rely on:
- LWC algorithm benchmarking as reference point to compare future results: including the report overhead in terms of silicon and power consumption.

- Specifications of countermeasures against fault attacks taking benefits from MRAM/CMOS hybridization properties: Attacks scenarii that can be faced with the help of permanent states stored in the logic will be fully documented.

- LWC algorithm designs: CMOS-based circuit as reference, hybridized and embedding MRAM-based coutermeasures: Design these non-volatile strengthening up to `place and route' on 28 nm FDSOI process. This hybridization approach can be built using NV process design kit. This is fully relevant as regard to ecosystems in STT-MRAM that is announced these days. As a result, the proposed circuits will be simulated (electrical, logic) to determine effective robustness of our solution against fault attacks as well as energy footprint compared to a CMOS built-in reference.

- Security characterization of the MRAM bitcells: It is mandatory to insure that innovation will not bring new vulnerabilities, or to mitigate these one.
The side-channel robustness will be evaluated on identified use cases. The power consumption traces will be estimated by simulation, challenged power analysis-based attacks and compared to the CMOS built-in reference. Vulnerabilities versus fault attacks will be characterized on dedicated samples (STT-MRAM bitcells) manufactured for the purpose of the project. They will be electrically characterized prior and after to any physical attack as Laser or Electromagnetic pulses. Modelization of the effects will be done and included in the simulation flow. Then a hardened STT-MRAM will be fabricated and validated following the same characterization sequence. To further improve this MRAM study, the SOT-MRAM (Spin Orbit Torque) will also be considered for simulations, nanofabrication and characterization.