Internet of Things (IoT) will play a major role in futuristic vehicle applications, such as vehicle-to-vehicle communications that reduce the chance of collision, advanced navigation systems that adjust the engine to features of the ground, predictive maintenance, partially autonomous vehicles, self-driving vehicles, etc. IoT relies on electronic systems that are capable of sensing, processing, and exchanging information. Guaranteeing the robustness, reliability, and maintainability of such electronic systems is a major challenge.
The EDITSoC project addresses this challenge from the perspective of Electrical Diagnosis (ED). Efficient diagnosis is essential for shedding light into the failure mechanisms that occur in electronic systems so as to apply corrective actions to prevent failure re-occurrence and hence increase safety and reliability features. The aim of this project is to develop concepts, methodologies, and tools towards a complete system-level diagnosis. More specifically, given a System-on-Chip (SoC) that has failed, the objective of the project is to develop a unified diagnosis flow that first pinpoints the IP block (or an interconnection between IP blocks) that has failed (i.e. system-level diagnosis) and secondly, if the failure is attributed to an IP block, output a list of potential defects within the IP block and rank these defects according to their probability of occurrence (i.e. IP block-level diagnosis).
Although the devised methodologies and tools can be used to diagnose SoCs that have failed during end-of-production test, the project mainly focuses on the diagnosis of SoCs that have failed during their mission mode, and for which a fast Failure Analysis (FA) is required and requested by the end-user in the context of customer returns.
Two metrics will be used to quantify the success rate of the project, namely the (a) Diagnosis Cycle Time (DCT) which refers to the time required to complete the diagnosis, starting from the customer returns to the complete identification of the root cause of the failure(s), and (b) the Resolution Metric (RM) which refers to the total die area occupied by the defect candidates that the proposed diagnosis flow outputs. The DCT metric allows quantifying the resulting speed up of diagnosis, whereas the RM metric allows quantifying the improvement in distinguishability and number of defect candidates identified during diagnosis.
The case studies used to validate the proposed solutions will be two large SoCs used in Advanced Driver Assistance Systems designed for automotive applications by STMicroelectronics in 55nm and 28nm technology nodes. More specifically, these SoCs target image recognition and treatment. They comprise heterogeneous digital and AMS IP blocks, including PLLs, ADCs, UARTs, I2C, SPI interfaces, Dual Data Rate 64bit controllers, parallel GPIO, Ethernet interface unit and on-chip processors. The use of two case studies is motivated by the need to show that the proposed diagnosis methodologies are technology independent.
Monsieur Patrick GIRARD (Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier)
The author of this summary is the project coordinator, who is responsible for the content of this summary. The ANR declines any responsibility as for its contents.
CNRS DR13-LIRMM Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier
LIP6 - UPMC Laboratoire d'informatique de Paris 6
ST STMicroelectronics SA
Help of the ANR 397,375 euros
Beginning and duration of the scientific project: December 2017 - 36 Months