Interferences in Design Methodology for High-performance Multi-Core Platforms – InterMCore
When a system is safety-critical, a certification activity must evaluate whether it is compliant with the appropriate standards in that domain. In the avionic and automotive domains, targeted by InterMCore, a key and open challenge is the safe and efficient use of heterogeneous high-performance multi-core platforms (e.g., ARM-based MPSoCs with accelerators), in particular when targeting next generation applications, mixing different criticality requirements and execution models. More precisely, the source of interferences between these applications must be identified and the interferences quantified and possibly reduced to master the temporal behavior of the system. While existing work often focuses on one aspect like identifying timing anomalies during the worst-case execution time computation or analyzing interferences caused by a single hardware component, there is a clear lack of a combined (software and hardware) methodology-aware flow which reasons about the effect of interference on complex MPSoCs to evaluate the predictability of the platform and provide means for interference mitigation.
The InterMCore project aims at building such an interference-centric methodology by: i) applying both formal methods and benchmarking to capture the timing behavior of these applications over an MPSoCs and ii) defining appropriate rules and transformations to guide the application software synthesis, from the programming model down to the execution platform, for an enhanced (i.e., more predictable) timing behavior with reduced interferences. A comprehensive framework for assessing but also mitigating the interferences generated by software executed over heterogeneous multi-core platforms will be developed, a key feature for efficiently design the next generation of safety-critical systems. Note that this proposal was submitted to the ANR PRCI 2021 call and comments from reviewers have been addressed, in particular narrowing the goals of the project and move the focus from certification to interferences in the proposed methodology (see cover letter for a more detailed analysis).
The INTERMCORE project combines expertise from French and German partners for: 1) identifying all sources of interference in heterogeneous high-performance MPSoCs (ONERA), 2) quantifying the effect of interference in terms of worst-case shared resources (communication and memory) delay using application loads and shared resources models (TU Dortmund), 3) identification of timing anomalies at the software level and considering formal models of the hardware (CEA) and 4) programming models and compilation techniques for a more predictable software and hardware mapping (TU Dresden). The consortium will target different classes of applications (e.g., control and DNN-based computer vision) from both the avionic (French side) and the automotive (German side) domains and will focus on the NXP S32V platform as a currently challenging and representative example for heterogeneous high-performance MPSoCs.
Monsieur Mathieu Jan (Laboratoire d'Intégration des Systèmes et des Technologies)
The author of this summary is the project coordinator, who is responsible for the content of this summary. The ANR declines any responsibility as for its contents.
ONERA Office National d'Etudes et de Recherches Aérospatiales
Université technique de Dortmund
LIST Laboratoire d'Intégration des Systèmes et des Technologies
Université technologique de Dresde
Help of the ANR 1,010,710 euros
Beginning and duration of the scientific project: March 2023 - 36 Months