Spintronic Ising Machine – SpinIM

Context:
The evolution of the modern information and communication society, trying to solve computing tasks of ever-increasing complexity and size, is expected to lead to energy consumption that will exceed the world’s energy production by 2040. This increase in energy consumption is related to the computing architectures requiring constant transfer of data between the memory and processing units (Von Neumann bottleneck). Therefore, it is essential and critical to search for innovation in computing hardware, architecture and algorithms as a common interdisciplinary co-design effort. Besides energy consumption, critical key issues for autonomous and embedded systems (smart sensors, edge artificial intelligence (AI)) are : speed, compactness and integrability.
Many innovative, low-energy hardware solutions take inspiration from biology and physics to solve efficiently complex computing tasks. One of the most promising directions is to emulate quantum or statistical physics paradigms to build innovative hardware systems able to solve combinatorial optimization problems, which still remain unsolvable on the existing digital hardware. Such problems (travelling salesman problems) can be found in all aspects of everyday life. In this aim, the Ising Machine is a promising approach based on the Ising-Hamiltonian of a network of coupled binary spins. Instead of using complex combinatorial schemes that suffer from the Von Neumann bottleneck between memory and processing, Ising Machines harness the inherent convergence of underlying Hamiltonian system towards energy minima. It thus allows an in-situ physics-driven convergence of the computing hardware to the solution of the mapped optimization problem.

Objective:
In this line of thinking, SpinIM aims to explore a spintronics-based, novel ultra-fast, energy-efficient, compact and scalable hardware approach for solving intensive combinatorial optimization problems. SpinIM will demonstrate an integrated spintronic Ising Machine at the nanoscale using spin-torque nano-oscillators coupled through electrical microwave currents. Through this first hardware proof-of-concept prototype, we will solve optimization tasks such as Maximum cut and graph coloring problems. To achieve this ambitious goal, we will control and program microwave couplings between spin-torque nano-oscillators using gate-controlled transistors in a monolithic CMOS-spintronic co-integrated architecture.

The overall methodology of SpinIM includes four main scientific steps:

(WP2) nanofabrication and design of three types of spin-torque nano-oscillator to emulate Ising spins (vortex-STNO, perpendicular MTJ-STNO, and three-terminal STNO).
(WP3) RF performance analysis of binary phase states and the stochastic phase-dynamics of single and coupled designed Ising spins, combined with the development of a simulation framework for the implementation of optimization algorithms.
(WP4) Implementation of reconfigurable Ising-spin network on RF-IC circuits on CMOS, tested for small-scale networks ( N<10 STNOs), co-integrated with the CMOS circuits.
(WP5) Implementation and definition of optimization problems solved by the Ising Machine Demonstrator combined with the computing approach's performance and scaling evaluation benchmark.

As an outcome, SpinIM will provide scientific and technical solutions that will open the path for building low-energy hardware for unconventional computing.

The project partners CEA-SPINTEC, and CEA-LETI come from cross disciplinary communities (spintronics and non-volatile memory CMOS integration), are leading experts in their research field and have been collaborating before.