Machinæ pluribus unum - (make) one machine out of many – Maplurinum
Cloud and high-Performance architectures are increasingly heteregenous and incorporate often specialized hardware. We have first seen the generalization of GPUs in the most powerful machines, followed a few years later by the introduction of FPGAs. More recently we have seen nascence of many other accelerators such as tensor processor units (TPUs) for DNNs or variable precision FPUs. Recent hardware manufacturing trends make it very likely that specialization will not only persist, but increase in future supercomputers. Because manually managing this heterogeneity in each application is complex and not maintainable, we propose in this project to revisit how we design both hardware and operating systems in order to better hide the heterogeneity to supercomputer users. In summary, we propose to rethink the hardware/software boundary in order to hide the heterogeneity behind a common minimal instruction set and a unified address space.
Project coordination
Gaël Thomas (Télécom SudParis)
The author of this summary is the project coordinator, who is responsible for the content of this summary. The ANR declines any responsibility as for its contents.
Partner
Inria Rennes - Bretagne Atlantique Centre de Recherche Inria Rennes - Bretagne Atlantique
LIST Laboratoire d'Intégration des Systèmes et des Technologies
TSP Télécom SudParis
TIMA Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés
Help of the ANR 730,727 euros
Beginning and duration of the scientific project:
March 2022
- 48 Months