Photonic Augmented Security via Physical Unclonable Functions – PHASEPUF

The development of photonic PUFs will be based on the following steps:
- design and exploration of various photonic architectures for weak and strong PUFs by means of circuit-level simulations taking into account fabrication tolerances into physical device-level simulations
- fabrication of the optimal architectures leveraging CMOS-compatible foundries
- characterization of the architectures by using an electro-optic testbed where different scenarios will be considered to assess their performance under fluctuations, aging, and electrical attacks
- experimental results analysis and comparison with simulations
The technologies that will be used for the various steps are:
- simulation tools such as lumerical interconnect and lumerical device to simulate the various architectures that are proposed in the PHASEPUF project. Python/matlab processing of the results will be used in conjunction with NIST statistical tests and ML modelling of the results as well as other common metrics (fractional Hamming distance/weight)
- CMOS-compatible platforms such as the silicon photonics platform of CEA-LETI for the fabrication featuring 300 nm thickness device layer and several building blocks such as high-speed modulators and detectors, grating couplers for input/output light coupling, and low-loss waveguides for light propagation
- electro-optic testbed for the characterization of the photonic chips including (vertical) optical coupling through grating coupler interfaces and on-wafer probes/electrical packaging to connect the chip to the FPGA driving
- high-performance servers will be used for analysis and modelling of the experimental data
To assess the robustness of the photonic PUFs various tools will be exploited:
- a temperature controlled chuck allowing to modify the temperature of the sample to emulate temperature fluctuations
- FPGA-based injection of electrical faults in the system
- near-field RF probes for electrical attacks
- on-wafer RF probes driven by an arbitrary waveform generator for device-level testing

To be updated

To be updated

F. Pavanello et al., «Recent advances in photonic physical unclonable functions,« IEEE ETS 2021, doi: 10.1109/ETS50041.2021.9465434

Recently, major security issues associated with the advancement of reverse engineering and cyber-attack techniques have emerged on a global scale, affecting hardware integrity and information security. In particular, counterfeit chips have been found in several defense and security systems, potentially capable of undermining system security and acquiring sensitive information or protected data. Physical unclonable functions (PUFs) are hardware solutions to combat counterfeiting at the circuit level and to generate cryptographic keys. They rely on the unpredictability of complex responses, highly dependent on manufacturing tolerances, and avoid local storage of keys in memory and thus the possibility that information is acquired by simple memory access through malware.
The most frequently used solutions are implemented in electronics using the manufacturing tolerances of transistors whose character is random and not clonable. Electronic approaches have several advantages such as their native implementation in CMOS technology and their flexibility to integrate with other systems. However, a certain degree of weakness against machine learning attacks has been demonstrated recently for these approaches because of their limited complexity in terms of degrees of freedom and their need for complex error correction units that consume a lot of power and surface area due to the classical limitations of transistors such as their ageing and temperature dependence. Concerning the other approaches studied to realize PUFs, several demonstrations using optics have been proposed, presenting very interesting performances in terms of randomness and richness of responses. Nonetheless, these approaches are often based on bulky optics with a low level of integration, which makes them expensive.
The PHASEPUF project aims at developing a new class of photonic PUFs, exploiting CMOS compatible platforms, and at demonstrating their advantages in terms of power consumption and compactness, as well as robustness and reliability, thanks to a greater richness of physical phenomena compared to electronic solutions based on the transfer of binary signals and subject to machine learning attacks.
Several architectures and methods of operation will be investigated during the project, favoring solutions with a high level of integration and which are compatible with low-cost mass production. These solutions will be evaluated with respect to electrical and machine learning attacks and their robustness and reliability will be studied by fault injection to emulate their ageing and behavior against temperature fluctuations.