CE24 - Micro et nanotechnologies pour le traitement de l’information et la communication

Non Volatile MRAM-based Asynchronous PROCessor – NV-APROC

Submission summary

The domain of integrated circuits and systems has been strongly driven by the advent of the Internet of Things and will continue to grow in the coming years. Constraints are strong, especially in terms of power consumption and autonomy, not only during computing phases, but also during standby or sleep phases. Circuit behavior will also have to meet new constraints mainly linked to changing energetic environment, automatic wake up on event, data storage and ultra-low supply voltage level. Such a circuit has to be completely autonomous according to its unstable environment, in terms of available and stored energy, still being in an optimum configuration of computation. ON/OFF computing strategy and Dynamic Power Management are necessary in many applications, especially in terms of power consumption and autonomy. To store and to access simultaneously an increasing amount of data, energy-efficient embedded architectures, processes and design techniques are required. However, the continuously decreasing size of devices and increasing operation frequency lead to high power consumption, which is a major challenge.

2016 was a turning point for MRAM (Magnetic RAM) memories, as its landscape has moved towards more industrial products & applications emphasized by recent announces. STT-MRAM (Spin Transfer Torque) flavor offers an excellent set of features to integrate future ultra-low power embedded systems. Integrating such devices into the computational logic is absolutely necessary, feasible and enables new energy-efficient architectures. Moreover, asynchronous design technique can significantly improve IoT domain circuits according to the duty cycle operation of IoT circuits for which a new paradigm has raised as normally-off computing.

NV-APROC main goal is to significantly decrease the power consumption of processors of about 1 order of magnitude of the total power consumption, by proposing a novel hybrid big – little clock-less non-volatile architecture. The targeted circuit will use the so-called asynchronous design technique, which is already well known to be energy efficient, and MRAM emerging non-volatile technology which has a really interesting set of features in terms of write / read energy. In order to demonstrate the potential of such an approach we propose to benchmark our innovative work up to full layout with state of the art synchronous version of the processor. By the end of the project we will highlight a complete study of several architectures providing the best way to go forward in a real breakthrough for ultra-low power applications.

Such an approach and study in a big-little processor architecture has never been addressed so far. In order to take the maximum benefits from the MRAM technology both STT, which is the most mature and studied worldwide, and SOT (Spin Orbit Torque), which is the most recent MRAM technology giving a very interesting set of features for high speed and low energy systems, will be considered and evaluated.

This project will strongly contribute to the preparation of the future electronics industry to extend the limits that mainstream technologies will be facing. NV-APROC is very ambitious and could have a huge added value, both on the storage and the computational abilities of connected objects, which are 2 critical parameters making barriers to the market. It will strengthen the technological know-how of the French and European Union in specific high added value types of IoT applications all along the value chain. There is an opportunity for Europe to become a major player in the field. On the other hand, many SMEs in France are working and focused on IoT applications for which the energy efficiency is a key factor. NV-APROC will promote the 28nm FD-SOI from STMicroelectronics and significant improvement on such processor architecture could interestingly highlight STMicroelectronics process. This project is supported by 4 French companies, very relevant in regards to the subject.

Project coordination

Grégory Di Pendina (Spintronique et Technologie des Composants)

The author of this summary is the project coordinator, who is responsible for the content of this summary. The ANR declines any responsibility as for its contents.

Partner

LETI Laboratoire d'Electronique et de Technologie de l'Information
SPINTEC Spintronique et Technologie des Composants
UM-LIRMM Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier

Help of the ANR 451,953 euros
Beginning and duration of the scientific project: September 2019 - 42 Months

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