CE24 - Micro et nanotechnologies pour le traitement de l’information et la communication

3D monolithically integrated SPAD pixels in advanced CMOS FDSOI technology – SPAD-FDSOI

3D monolithically integrated SPAD pixels in advanced CMOS FDSOI 28nm technology

This project meets the performance needs of photodetectors (response time, sensitivity, etc.) for applications such as 3D vision, for example facial recognition or navigation aid, medical imaging, etc. but also for potential new applications in cryptography or photonics / quantum optics.

Towards a monolithic 3D SPAD integrated pixel

The main objective of the ANR SPAD-FDSOI project is to study the feasibility of integrating photodiodes operating in Geiger mode, that is to say at a reverse bias beyond the breakdown voltage (called SPAD Single Photon Avalanche Diode) in a very advanced commercial microelectronics technology 28 nm CMOS FDSOI (Fully Depleted Silicon-on-Insulator) available from the founder STMicroelectronics. This SPAD-FDSOI architecture has the advantage of producing an intrinsically 3D pixel at chip level (without recourse to stack at wafer level), with an optimal fill factor and the possibility of combining high-performance electronics for the detection of events. , addressing at matrix level, data processing, etc

The work focuses on the architecture of the photodiode itself and its associated electronic circuitry. The design phase uses TCAD simulation tools, additional tools developed in-house, integrated circuit design platforms with the PDK provided by the foundry (from diagram to layout). Manufacturing is managed by the CMP within the framework of multi-project circuits (MPW). In addition, the integration of prototypes requires specific developments such as die thinning, transfer of individual chips, etc. The electro-optical characterization includes the electrical response in the dark (breakdown voltage, dark count rate), the response under illumination (spectral response and detection efficiency, response time).

Work and results obtained:
- Measurements carried out on a previous test-chip: noise reduction (DCR - Dark Count Rate) with an adapted geometry of STI trench (Shallow Trench Isolation) at the edge of the active zone, comparison with simulations and improvement of predictive simulation methods, demonstration of indirect avalanche detection.
- Study of original electronic architectures for avalanche detection and quenching using the full potential offered by CMOS28FDSOI technology.
- Design of 2 integrated circuits / test-chips in the fall of 2019: a circuit dedicated to the study of the SPAD architecture itself and a circuit dedicated to the associated electronics.
- Extreme thinning of SPAD chips/dies for operation in Back-Side Illumination mode: development of the temporary bonding process for chips on the handle and ring allowing a solid surface to be reconstituted, carrying out the first extreme thinning (between 10 and 20 µm) , development of the method of transferring the thinned chips onto a substrate allowing the test.

Key facts and results (June 2020 at mid-term)
- Reduced noise with an adapted STI trench geometry.
- Demonstration of indirect avalanche detection.
- Study of original electronic architectures for avalanche detection and quenching. The pixel architectures proposed and integrated in the first circuit are state of the art from the point of view of the extinction speed (pixel capable of detecting the avalanche in less than 30ps and of completely extinguishing the avalanche in less than 300ps). The integration of broadband analog monitoring of the SPAD should provide new information on its behavior and rethink the simulation models of the SPADs.
- Demonstration of the feasibility of thinning individual chips below 20 µm without crippling damage with the original method proposed.

Work forecasts and prospects:
- Electrical and opto-electrical measurements of the two SPAD FDSOI test-chips and analysis of the results.
- The circuits / test-chips should be delivered before the end of the calendar year 2020. The test printed-circuit boards allowing to assemble and characterize the integrated circuits are in manufacture and should be available during the month of October 2020. The first characterizations should therefore be able to be carried out before the end of 2020 and to be finalized at the beginning of 2021. In the meantime, a second circuit is being designed with 2 new pixel architectures which makes it possible to place the control electronics above the SPAD in order to take advantage of the intrinsic 3D approach.
- Nanostructuring study to improve detection efficiency (PDP): development of simulation and estimation methodology for PDP (optical and electrical coupling).
- Transfer of the first functional SPAD chips on a glass substrate and first opto-electrical tests in BSI mode.

Body-biasing considerations with SPAD FDSOI: advantages and drawbacks
T. Chaves de Albuquerque, D. Issartel, R. Clerc, P. Pittet, R. Cellier, W. Uhring, A. Cathelin, F. Calmon
ESSDERC 2019, 23-26 sept. 2019, Cracovia, Poland (http://dx.doi.org/10.1109/ESSDERC.2019.8901825)

An Ultrafast Active Quenching Circuit for SPAD in CMOS 28nm FDSOI Technology
Mohammadreza DOLATPOOR LAKEH, Jean-Baptiste KAMMERER, Wilfried UHRING, Jean-Baptiste SCHELL, Francis CALMON
SENSORS 2020, October 25-28, 2020 (virtual conference)

Indirect Avalanche Event Detection of Single Photon Avalanche Diode Implemented in CMOS FDSOI Technology
T. Chaves de Albuquerque, D. Issartel, R. Clerc, P. Pittet, R. Cellier, D. Golanski, S. Jouan, A. Cathelin, F. Calmon
Elsevier Solid-State Electronics Volume 163, January 2020, p. 107636 (https://doi.org/10.1016/j.sse.2019.107636)

Lowering the Dark Count Rate of SPAD Implemented in CMOS FDSOI Technology
T. Chaves de Albuquerque, D. Issartel, R. Clerc, P. Pittet, R. Cellier, F. Calmon
ULIS-EUROSOI 2019, 1-3 April 2019, Grenoble, France (https://doi.org/10.1109/EUROSOI-ULIS45800.2019.9041916)

SPAD FDSOI cell optimization for lower dark count rate achievement
D. Issartel, T. Chaves de Albuquerque, R. Clerc, P. Pittet, R. Cellier, D. Golanski, A. Cathelin, F. Calmon
ULIS-EUROSOI 2020, Sept. 2020 (virtual conference)

Single-Photon Avalanche Diodes (SPAD) have been widely studied and successfully implemented for the detection of weak optical signals in the visible and near-infrared spectrum range (NIR). They are able of capturing individual photons with typically sub-nanosecond timing resolution, which make them suitable for a wide area of application such as low light detection, time of flight measurements (e.g. telemeter) and more recently in quantum random number generators.
The use of CMOS technologies allows low-cost, compact and reliable implementation of SPADs. Thus, CMOS SPAD-based sensors enter rapidly the consumer market. However, for more demanding applications such as image sensors (for 3D and/or time-resolved imaging), several technological challenges still need to be tackled. The current research efforts are mainly focusing on the increase of the fill factor and the photon detection efficiency for NIR photons. One way to keep the CMOS compatibility is to implement SPAD-based sensors with 3D-stacking of two tiers; one hosting the SPADs (with backside illumination), the other one hosting the associated electronics.
SPAD-FDSOI research program aims at developing high performances - high fill-factor SPAD pixel integrated in advanced standard CMOS technology. The key idea is to use some specific features of advanced CMOS 28nm FDSOI (Fully Depleted Silicon-on-Insulator) technology to develop a novel 3D monolithically integration of SPAD pixel with back-side illumination. The expected benefits of such an integration are much higher fill factor (>50%), with state of-the-art performances (Dark Count Rate - DCR, Photon Detection Probability - PDP, spatial and time resolutions), low power resulting from the FDSOI technology choice and a cost effective and reliable solution for 3D SPAD and associated electronics implementation due to the monolithically integration (no need of staking two tiers). In this novel approach for SPAD integration, the avalanche diode is implemented beneath the buried oxide using the existing doped layers (used for transistor back-biasing) while the associated electronics (quenching and addressing) is implemented in the ultra-thin top silicon layer (this concept has been proposed by the present coordinator in 2017, preliminary simulation study has been published, first very encouraging experimental results has been submitted for publication at ESSDERC 2018 conference).
This project is proposed by INL (coordinator), ICube and CEA-LETI. Altogether, these partners gather all the know-how, expertise, and tools to successfully realize the ambitious goal of this project. The project is organized with three scientific work packages WP1-2-3 (and “management and dissemination” work package WP0). WP1 (driven by INL) will focus on the optimization and design of the SPAD cell (from of TCAD simulations to SPAD active region layout). Additionally, WP1 will investigate the photonics concepts of “light trapping” to increase the PDP for NIR light. WP2 (driven by ICube) will include IC design with SPAD array and integrated electronics (quenching, addressing, processing) and characterizations (static / dynamic, dark / illuminated properties). Results of prototype characterization will be included in the modeling and design refinement feedback loop. WP3 (driven by CEA-LETI) is dedicated to technological developments i) die thinning for back-side illumination, ii) proposal of additional technological steps for the implementation of the light trapping concept.
Moreover STMicroelectronics Crolles has already supported this project with a free access to a multi-project wafer run in 2017 (CMOS28FDSOI technology).
The results of this program on 3D monolithically integration of SPAD pixels in FDSOI could be considered for a rapid industrial transfer towards companies such as STMicroelectronics which is a major player in the field of SPAD for mass-market: proximity sensor in mobile phone, LIDAR, driving assistance for automotive, drone etc.

Project coordinator

Monsieur Francis Calmon (Institut des Nanotechnologies de Lyon)

The author of this summary is the project coordinator, who is responsible for the content of this summary. The ANR declines any responsibility as for its contents.

Partner

CEA - LETI Commissariat à l'énergie atomique et aux énergies alternatives
INL-CNRS Institut des Nanotechnologies de Lyon
ICube Laboratoire des sciences de l'Ingénieur, de l'Informatique et de l'Imagerie

Help of the ANR 525,347 euros
Beginning and duration of the scientific project: - 42 Months

Useful links

Explorez notre base de projets financés

 

 

ANR makes available its datasets on funded projects, click here to find more.

Sign up for the latest news:
Subscribe to our newsletter