New hybrid integration technology of a multilevel interleaved inverter under thermal and EMC constraints with fail safe and redundant capability – HIT-TEMS
The aim of the project HIT-TEMS consists in a PCB (Printed Circuit Board) integration of a safety parallel multi-level inverter dedicated to embedded applications. In this context, the volume and the weight are preponderant and the converter must be able to operate in harsh operating conditions: strong variations of temperature (-40°C/150°C) under a sensitive electromagnetic environment (proximity calculators). In this project, process integration of passive components (magnetics and dielectrics), active components (semi-conductors and drivers) and buried sensors inside PCB will be developed. Thermal and EMC constraints as well as fail-safe behavior will be taken into account in each step of conception. Technological bricks and prototypes integrating these constraints will be developed step by step along the project and a final prototype will be developed to demonstrate the capability of the multi-levels inverter to be integrated. Its performances will be evaluated in terms of power density and compared with a classical two levels inverter (associated to its EMC filter and its heat sink).
Monsieur Denis Labrousse (Systèmes et applications des technologies de l'information et de l'énergie)
The author of this summary is the project coordinator, who is responsible for the content of this summary. The ANR declines any responsibility as for its contents.
SATIE Systèmes et applications des technologies de l'information et de l'énergie
Help of the ANR 374,400 euros
Beginning and duration of the scientific project: December 2015 - 48 Months