JCJC SIMI 9 - JCJC - SIMI 9 - Sciences de l'Ingénierie, Matériaux, Procédes et Energie

Ultimate power multi-switching cells system integration in silicon multi-poles chip. – ConvPlUS

Submission summary

The project deals with the integration in the field of power electronics. It aims at developing new quasi-monolithic or monolithically integrated silicon power switching cells of higher performance and reliability. More precisely, The project aims to demonstrate through technological realisations two new integration approaches of inverter bridge legs in order to reduce the number of discrete silicon chips in a power module making it possible to reduce or suppress wire-bondings as well parasitic coupling capacitances. That will lead to performance as well as reliability improvement.
The strategies that we propose for improving the performance and reliability of power modules are new in the sense that they combine both the monolithic and hybrid integration approaches for the optimisation of the entire system. Indeed, generally the followed optimisation approaches focus either on the silicon chip or on the packaging. Interconnection technologies were developed for wire-bonding reduction. However, the technology of realisation is generally very complex.
For low power applications (few hundreds of Watts), the monolithic integration of power conversion functions and their driving circuitry can be carried-out through the use of lateral power devices. This integration approach is unfortunately restricted to some applications such as : household appliances and auxiliary power functions. It has however the advantage of allowing wire bonding reduction and it allows a collective fabrication of the power function.
For medium power applications (few kW to few 10 kW), the use of vertical power devices is necessary. The vertical devices extend from the upper side of the silicon wafer down to the lower side. When many vertical power devices share the same silicon chip, their drift regions (lightly doped) are not electrically isolated from each other. In this project, a technique based on the use of vertical boron highly walls will be developed.
To that end, we have recently started research works on the design and realisation of new multi-switch silicon chips. The integrated switches have a vertical architecture. We intend to set up new solutions that will permit the realisation of power switching cells by assembling the minimum number of power silicon chips as compared to the classical approach. We first target to design and realise new complementary multi-switch silicon chips : common anode and common cathode multi-switch cells. Then we merge the two complementary multi-switch chips in order to devise and realise a monolithic macro-chip of a particular architecture. The complementary power silicon chips as well as the compact packaging will be optimised simultaneously in a system optimisation approach that targets generic applications and laboratory prototypes. The single macro-chip integration approach is the most ambitious approach due to the technological challenges for its realisation. However, if the fixed objective of realising the macro mono-chip is reached, this structure will be for us the ultimate integration and will be very attractive from the applications point of view.

Project coordination

Abdelhakim BOURENNANE (Laboratoire d'Analyse et d'Architecture des Systèmes) – abourenn@laas.fr

The author of this summary is the project coordinator, who is responsible for the content of this summary. The ANR declines any responsibility as for its contents.

Partner

LAAS Laboratoire d'Analyse et d'Architecture des Systèmes

Help of the ANR 374,279 euros
Beginning and duration of the scientific project: October 2013 - 48 Months

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