Architectures FPGA hiérarchiques sécurisées pour les systèmes sur puce – SEFPGA

The economical constraints linked to the cost and market adaptation impose the integration of processor
cores in the VLSI circuits. The flexibility that the System on a Chip "SoC" provides, suffers from a lack of
performances for certain classes of application which need both speed and flexibility. For instance a
cryptoprocessor able to run different cryptographic functions is penalized by a 100% software
computation. A reconfigurable hardware structure offers an interesting trade-off: on the one hand, it
allows to meet the calculation speed and on the other hand, it permits the adaptation to the user needs.
The choice of an embedded Field Programmable Gate Array (e-FPGA) structure for cryptographic needs
is sensible because it allies adaptability and performances. But as any hardware cryptoprocessor, the e-
FPGA can be the target of physical attacks or "side channel" attacks. For instance the Differential Power
Analysis (noted "DPA") consists in analyzing the consumed current on the power supply line. The secret
(the key) is deduced when correlating the measurement traces with signature predictors corresponding
to key subsets.
The e-FPGA must then be on one's guard against the attacks by integrating efficient countermeasures in
both the intrinsic structure and the programmed application. It has turned out that its generic structure
offers multiple ways to fight against attacks. A first level concerns the cell and the interconnect
architecture which can be optimized to reduce the leakage from the side channels. An example is to use
so-called dual rail signals to balance the power consumption. A second level is the programmed netlist
which can integrate logic countermeasures like those proposed in ASIC chips. A third level is based on
the netlist change which can take advantage of dynamic reconfiguration to impede the attacks.
will be studied. This structure which is called "hierarchical" or "tree", as opposed to matrix or "mesh"
structures used in commercial FPGAs, can offer multiple advantages. It has notably been proven at the
LIP6 laboratory that this interconnection class allowed to gain 40% of area with respect to the mesh
structure. However this tree structure can be more difficult to route than the regular matrix. An
architectural study associated with a layout design in ASIC standard cell technology will permit to answer
both the routability question and to weight the modification cost imposed for security reasons. The
evaluation of the FPGA cell architecture, along with the interconnection, need the design of specific CAD
tools to place and route different topological configurations and different level of security. The security
study on the tree architecture will be supported by recent works lead at ENST about the mesh e-FPGA.
The physical security study will be carried out by means of different layout scenarios. A chosen
architecture will be designed in an ASIC prototype chip. This chip will be finally evaluated functionally
and tested with different countermeasures on the ENST attack platform.
In conclusion this project aims at demonstrating the feasibility and the assets of a secured embedded
FPGA (SeFPGA) based on a hierarchical interconnection structure. From a theoretical point of view this
solution allows to reduce the number of switches and hence to optimize the silicon area and speed. The
project will consist first in making the architecture secured and second in designing a prototype chip to
validate both the tree structure and the countermeasures. CAD tools will be developed in order to
converge towards an optimal topology and to allow the users to take advantage of this new structure.
These tools will permit to use securing methods at all levels of the design flow and with generic security
parameter such –-secure=<n>, where <n> is the degree of security.